Logic chip including embedded magnetic tunnel junctions
First Claim
1. An apparatus comprising:
- a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer;
a first spacer; and
a first Inter-Layer Dielectric (ILD) material;
wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance;
wherein the first spacer, having a first maximum width no wider than the first horizontal offset distance, directly contacts at least one of the first upper MTJ layer and the first tunnel barrier;
wherein a first horizontal plane, which is parallel to the first lower surface, intersects a first polish stop material that is included between the first MTJ and the first ILD material;
wherein (a) the first ILD material includes silicon and oxygen, (b) the first lower MTJ layer includes cobalt, iron, boron, and ruthenium, (c) the first tunnel barrier includes magnesium and oxygen, (d) the first upper MTJ layer includes cobalt, iron, boron, ruthenium, and tantalum, (e) the first spacer includes silicon and oxygen, and (f) the first polish stop material includes silicon and nitrogen.
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Accused Products
Abstract
An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
27 Citations
24 Claims
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1. An apparatus comprising:
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a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer; a first spacer; and a first Inter-Layer Dielectric (ILD) material; wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance; wherein the first spacer, having a first maximum width no wider than the first horizontal offset distance, directly contacts at least one of the first upper MTJ layer and the first tunnel barrier; wherein a first horizontal plane, which is parallel to the first lower surface, intersects a first polish stop material that is included between the first MTJ and the first ILD material; wherein (a) the first ILD material includes silicon and oxygen, (b) the first lower MTJ layer includes cobalt, iron, boron, and ruthenium, (c) the first tunnel barrier includes magnesium and oxygen, (d) the first upper MTJ layer includes cobalt, iron, boron, ruthenium, and tantalum, (e) the first spacer includes silicon and oxygen, and (f) the first polish stop material includes silicon and nitrogen. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An apparatus comprising:
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a monolithic substrate; a memory area, comprising a magnetic tunnel junction (MTJ) that includes a tunnel barrier directly contacting lower and upper MTJ layers, located on the substrate; and a logic area located on the substrate; wherein a horizontal plane, which is parallel to the tunnel barrier, intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area; wherein the first ILD material includes a first chemical composition and the second ILD material includes a second chemical composition unequal to the first chemical composition; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer sidewall by a horizontal offset space that defines a horizontal offset distance; wherein (a) the first ILD material includes silicon and oxygen, (b) the first lower MTJ layer includes cobalt, iron, boron, and ruthenium, (c) the first tunnel barrier includes magnesium and oxygen, and (d) the first upper MTJ layer includes cobalt, iron, boron, ruthenium, and tantalum. - View Dependent Claims (14, 15, 16, 17)
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18. An apparatus comprising:
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a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer; a first spacer; and a vertical MTJ layer portion, an additional vertical MTJ layer portion, and a vertical tunnel barrier portion directly contacting the vertical MTJ layer portion and the additional vertical MTJ layer portion; wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance; wherein the first spacer, having a first maximum width no wider than the first horizontal offset distance, directly contacts at least one of the first upper MTJ layer and the first tunnel barrier; wherein the vertical MTJ layer portion, the additional vertical MTJ layer portion, and the vertical tunnel barrier portion are all between logic and memory areas included in the apparatus and are all intersected by a first horizontal plane; wherein (a) the first lower MTJ layer includes cobalt, iron, boron, and ruthenium, (b) the first tunnel barrier includes magnesium and oxygen, (c) the first upper MTJ layer includes cobalt, iron, boron, ruthenium, and tantalum, and (e) the first spacer includes silicon and oxygen. - View Dependent Claims (19, 20, 21)
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22. An apparatus comprising:
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a first magnetic tunnel junction (MTJ) including a first upper MTJ layer, a first lower MTJ layer, and a first tunnel barrier directly contacting a first lower surface of the first upper MTJ layer and a first upper surface of the first lower MTJ layer; a first spacer; and a first hardmask directly contacting a first upper surface of the first upper MTJ layer and the first spacer; wherein the first upper MTJ layer includes a first upper MTJ layer sidewall and the first lower MTJ layer includes a first lower MTJ sidewall horizontally offset from the first upper MTJ layer sidewall by a first horizontal offset space that defines a first horizontal offset distance; wherein the first spacer, having a first maximum width no wider than the first horizontal offset distance, directly contacts at least one of the first upper MTJ layer and the first tunnel barrier wherein (a) the first lower MTJ layer includes cobalt, iron, boron, and ruthenium, (b) the first tunnel barrier includes magnesium and oxygen, (c) the first upper MTJ layer includes cobalt, iron, boron, ruthenium, and tantalum, (d) the first hardmask includes tantalum, and (e) the first spacer includes silicon and oxygen. - View Dependent Claims (23, 24)
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Specification