Semiconductor devices, FinFET devices and methods of forming the same

• US 9,997,633 B2
• Filed: 03/16/2016
• Issued: 06/12/2018
• Est. Priority Date: 10/02/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsiao, Ru-Shang, Wu, Chii-Ming
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US15/071,206
• Publication Number:
  US 20170098711A1
• Time in Patent Office: 818 Days
• Field of Search: 257330
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate over the substrate. Besides, the gate include a first portion, a second portion overlying the first portion and a third portion overlying the second portion, and the critical dimension of the second portion is smaller than each of the critical dimension of the first portion and the critical dimension of the third portion.

Claims

1. A semiconductor device, comprising:

a substrate; and

a gate over the substrate,

wherein the gate comprises a first portion, a second portion overlying the first portion and a third portion overlying the second portion, and a critical dimension of the second portion is smaller than each of a critical dimension of the first portion and a critical dimension of the third portion,

wherein the critical dimension of the third portion is greater than the critical dimension of the first portion.

2. The semiconductor device of claim 1, wherein the substrate is a substrate with at least one fin extending in a first direction, and the gate extends in a second direction different from the first direction and is across the at least one fin.

3. The semiconductor device of claim 1, wherein the substrate is a planar substrate.

4. The semiconductor device of claim 1, wherein the gate further comprises a fourth portion between the first portion and the second portion, and the critical dimension of the fourth portion is smaller than the critical dimension of the first portion while greater than the critical dimension of the second portion.

5. The semiconductor device of claim 4, wherein the gate further comprises a fifth portion between the second portion and the third portion, and the critical dimension of the fifth portion is between the critical dimension of the second portion and the critical dimension of the third portion.

6. The semiconductor device of claim 5, wherein the critical dimension of the fourth portion is less than the critical dimension of the fifth portion.

7. The semiconductor device of claim 1, further comprising spacers on sidewalls of the gate, wherein the spacers comprise a nitrogen-containing dielectric material, a carbon-containing dielectric material or both, and the spacers have a dielectric constant less than about 10.

8. The semiconductor device of claim 1, wherein the gate comprises a silicon-containing material, a metal-containing material or a combination thereof.

9. A FinFET device, comprising:

a substrate having at least one fin;

a gate disposed across the at least one fin and having a narrow-middle profile that is narrow in a middle portion thereof, wherein the middle portion of the gate is no higher than half of a height of the gate,

wherein the gate further has a top portion and a bottom portion that are wider than the middle portion, and a critical dimension of the top portion is greater than a critical dimension of the bottom portion.

10. The FinFET device of claim 9, further comprising spacers on sidewalls of the gate, wherein the spacers comprise a nitrogen-containing dielectric material, a carbon-containing dielectric material or both, and the spacers have a dielectric constant less than about 10.

11. The FinFET device of claim 10, further comprising source/drain regions at two sides of the gate, wherein sidewalls of the source/drain regions in the substrate are inclined away from bottoms of the spacers.

12. The FinFET device of claim 11, further comprising contacts above the source/drain regions, wherein bottom surfaces of the contacts are no higher than the middle portion of the gate.

13. A method of forming a FinFET device, comprising:

providing a substrate with at least one fin;

forming a dummy layer on the substrate covering the at least one fin;

forming a mask layer on the dummy layer;

performing at least one main etching step and at least one lateral etching step to the dummy layer by using the mask layer as an etch mask, so as to form a dummy gate with a narrow-middle profile and a substantially smooth sidewall contour;

forming source/drain regions at two sides of the dummy gate; and

replacing the dummy gate with a gate, wherein the gate comprises a bottom portion, a middle portion and a top portion, wherein a critical dimension of the middle portion is smaller than each of a critical dimension of the bottom portion and a critical dimension of the top portion, and the critical dimension of the top portion is greater than the critical dimension of the bottom portion.

14. The method of claim 13, wherein each of the at least one main etching step and the at least one lateral etching step comprises an anisotropic etching, an isotropic etching, a reactive ion etching (RIE) process, or a combination thereof.

15. The method of claim 13, further comprising, after the step of forming the dummy gate and before the step of forming the source/drain regions, forming spacers on sidewalls of the dummy gate, wherein the spacers comprise a nitrogen-containing dielectric material, a carbon-containing dielectric material or both, and the spacers have a dielectric constant less than about 10.

16. The method of claim 15, wherein the spacers are formed conformally along the sidewalls of the dummy gate.

17. The method of claim 13, the step of replacing the dummy gate with the gate comprises:

forming a dielectric layer aside the dummy gate;

removing the dummy gate to form a trench in the dielectric layer; and

forming the gate in the trench.