Package programmable decoupling capacitor array
First Claim
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1. A semiconductor chip, comprising:
- an integrated circuit disposed on a packaging substrate; and
a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate,whereinthe programmable connectivity array comprises discrete blocks of on-die programmable decoupling capacitors formed on the semiconductor chip,multiple electrically conductive bumps are disposed on each block of the discrete blocks and are connectable to the power distribution network,a specified capacitance is obtainable by connecting a first subset of the discrete blocks of the on-die programmable decoupling capacitors to the power distribution network and the integrated circuit via the packaging substrate while a second subset of the discrete blocks of the on-die programmable decoupling capacitors remains unconnected, andthe first subset of the discrete blocks of the on-die programmable decoupling capacitors is configured to serve as a band rejection filter, and a frequency of the band rejection filter is controllable as a function of a first number of the first subset of the discrete blocks and a second number of the electrically conductive bumps used to connect each block of the first subset of the discrete blocks to the power distribution network.
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Abstract
A semiconductor chip allows for a selected amount of on-die decoupling capacitance to be connected to a very-large-scale integrated circuit (VLSI) system after the circuit design is complete. The semiconductor chip comprises an integrated circuit disposed on a packaging substrate, and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate.
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Citations
20 Claims
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1. A semiconductor chip, comprising:
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an integrated circuit disposed on a packaging substrate; and a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate, wherein the programmable connectivity array comprises discrete blocks of on-die programmable decoupling capacitors formed on the semiconductor chip, multiple electrically conductive bumps are disposed on each block of the discrete blocks and are connectable to the power distribution network, a specified capacitance is obtainable by connecting a first subset of the discrete blocks of the on-die programmable decoupling capacitors to the power distribution network and the integrated circuit via the packaging substrate while a second subset of the discrete blocks of the on-die programmable decoupling capacitors remains unconnected, and the first subset of the discrete blocks of the on-die programmable decoupling capacitors is configured to serve as a band rejection filter, and a frequency of the band rejection filter is controllable as a function of a first number of the first subset of the discrete blocks and a second number of the electrically conductive bumps used to connect each block of the first subset of the discrete blocks to the power distribution network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 17)
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9. A method of suppressing supply noise in a semiconductor chip, comprising:
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placing a programmable connectivity array physically near an integrated circuit embedded in a semiconductor chip, wherein the programmable connectivity array comprises discrete blocks of on-die programmable decoupling capacitors formed on the semiconductor chip, the semiconductor chip is supported on a packaging substrate, and multiple electrically conductive bumps are disposed on each block of the discrete blocks; connecting a first subset of the discrete blocks of the on-die programmable decoupling capacitors to the integrated circuit and a power distribution network of the semiconductor chip to obtain a target capacitance, wherein the connecting causes a second subset of the discrete blocks of the on-die programmable decoupling capacitors to remain unconnected, the first subset of the discrete blocks is configured to serve as a band rejection filter, and the connecting comprises setting a frequency of the band rejection filter as a function of a first number of the first subset of the discrete blocks and a second number of the electrically conductive bumps used to connect each block of the first subset of the discrete blocks to the power distribution network; and supplying power to the integrated circuit via the first subset of the discrete blocks through the packaging substrate. - View Dependent Claims (10, 11, 12, 15, 16)
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13. A method of suppressing resonant peaks in an integrated circuit in a semiconductor chip, comprising:
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supporting the semiconductor chip on a packaging substrate; and supplying power to the integrated circuit via a programmable connectivity array through the packaging substrate, wherein the programmable connectivity array comprises a first subset of discrete blocks of on-die programmable decoupling capacitors that are formed on the semiconductor chip, the first subset being a selectable number of the discrete blocks, smaller than a total number of the discrete blocks, that correspond to a defined capacitance, a second subset of the discrete blocks of on-die programmable decoupling capacitors remain unconnected, the discrete blocks are placed physically near the integrated circuit, the first subset of the discrete blocks form a band rejection filter of the semiconductor chip, multiple electrically conductive bumps are formed on each block of the discrete blocks of on-die programmable decoupling capacitors, and a frequency of the band rejection filter is configurable as a function of the number of the first subset of the discrete blocks and a number of the electrically conductive bumps through which the power is supplied to the integrated circuit. - View Dependent Claims (14, 18, 19, 20)
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Specification