×

Package programmable decoupling capacitor array

  • US 9,998,100 B2
  • Filed: 08/28/2015
  • Issued: 06/12/2018
  • Est. Priority Date: 08/28/2015
  • Status: Active Grant
First Claim
Patent Images

1. A semiconductor chip, comprising:

  • an integrated circuit disposed on a packaging substrate; and

    a power distribution network that is electrically connectable to the integrated circuit via a programmable connectivity array via the packaging substrate,whereinthe programmable connectivity array comprises discrete blocks of on-die programmable decoupling capacitors formed on the semiconductor chip,multiple electrically conductive bumps are disposed on each block of the discrete blocks and are connectable to the power distribution network,a specified capacitance is obtainable by connecting a first subset of the discrete blocks of the on-die programmable decoupling capacitors to the power distribution network and the integrated circuit via the packaging substrate while a second subset of the discrete blocks of the on-die programmable decoupling capacitors remains unconnected, andthe first subset of the discrete blocks of the on-die programmable decoupling capacitors is configured to serve as a band rejection filter, and a frequency of the band rejection filter is controllable as a function of a first number of the first subset of the discrete blocks and a second number of the electrically conductive bumps used to connect each block of the first subset of the discrete blocks to the power distribution network.

View all claims
  • 9 Assignments
Timeline View
Assignment View
    ×
    ×