Techniques for low complexity turbo product code decoding
First Claim
1. An apparatus for decoding, comprising:
- a memory;
a processor coupled to the memory, the processor configured to;
obtain a first message comprising a plurality of information bits and a plurality of parity bits, wherein the first message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors;
perform an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message;
determine if the iterative TPC decoding was successful; and
upon determining that the TPC decoding was not successful, determine one or more error locations in the second message based on a third constituent code using a third decoder, wherein the third decoder determines the one or more error locations in a predefined number of clock cycles based on an additional iterative TPC decoding on the second message, wherein the additional iterative TPC decoding comprises;
generating a syndrome of the third constituent code in an initial iteration based on the second message;
updating a value of the syndrome by at least using the one or more error locations determined in the initial iteration; and
decoding the second message in a next iteration based on the updated value of the syndrome.
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Abstract
Techniques are described for decoding a codeword, including, obtaining a first message comprising a plurality of information bits and a plurality of parity bits, wherein the message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors, performing an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message, determining if the decoding was successful. Upon determining that the TPC decoding was not successful, determining one or more error locations in the second message based on a third constituent code using a third decoder. The third decoder determines the one or more error locations in a predetermined number of clock cycles.
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Citations
20 Claims
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1. An apparatus for decoding, comprising:
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a memory; a processor coupled to the memory, the processor configured to; obtain a first message comprising a plurality of information bits and a plurality of parity bits, wherein the first message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors; perform an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message; determine if the iterative TPC decoding was successful; and upon determining that the TPC decoding was not successful, determine one or more error locations in the second message based on a third constituent code using a third decoder, wherein the third decoder determines the one or more error locations in a predefined number of clock cycles based on an additional iterative TPC decoding on the second message, wherein the additional iterative TPC decoding comprises; generating a syndrome of the third constituent code in an initial iteration based on the second message; updating a value of the syndrome by at least using the one or more error locations determined in the initial iteration; and decoding the second message in a next iteration based on the updated value of the syndrome. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for decoding, comprising:
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obtaining a first message comprising a plurality of information bits and a plurality of parity bits, wherein the first message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors; performing an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message; determining if the iterative TPC decoding was successful; and upon determining that the TPC decoding was not successful, determining one or more error locations in the second message based on a third constituent code using a third decoder, wherein the third decoder determines the one or more error locations in a predefined number of clock cycles based on an additional iterative TPC decoding on the second message, wherein the additional iterative TPC decoding comprises; generating a syndrome of the third constituent code in an initial iteration based on the second message; updating a value of the syndrome by at least using the one or more error locations determined in the initial iteration; and decoding the second message in a next iteration based on the updated value of the syndrome. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A non-transitory processor-readable medium for decoding, comprising processor-readable instructions configured to cause one or more processors to:
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obtain a first message comprising a plurality of information bits and a plurality of parity bits, wherein the first message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors; perform an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message; determine if the iterative TPC decoding was successful; and upon determining that the TPC decoding was not successful, determine one or more error locations in the second message based on a third constituent code using a third decoder, wherein the third decoder determines the one or more error locations in a predefined number of clock cycles based on an additional iterative TPC decoding on the second message, wherein the additional iterative TPC decoding comprises; generating a syndrome of the third constituent code in an initial iteration based on the second message; updating a value of the syndrome by at least using the one or more error locations determined in the initial iteration; and decoding the second message in a next iteration based on the updated value of the syndrome. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification