High speed transmission receiver utilizing fine receiver timing and carrier phase recovery

• US RE28,638 E
• Filed: 09/25/1974
• Issued: 12/02/1975
• Est. Priority Date: 03/18/1971
• Status: Expired

• Current Assignee: N/A
• Original Assignee: N/A
• Application Number:
  US05/508,927
• Time in Patent Office: 433 Days
• US Class Current: 375/232
• CPC Class Codes: N/A

Abstract

The invention is directed to an improvement in a digital data receiver of the type which utilizes an adaptive equalizer having a plurality of adjustable attenuators to remove distortion in received signals. The improvement comprises a system which utilizes the signals available at the equalizer adjustable attenuators to achieve accurate and stable carrier phase and timing control signals.

Claims

1. In combination with a high speed digital data receiver having a transversal equalizer with multiple adjustable attenuators, the improvement comprising:

a first comparator connected to the output of at least two adjustable attenuators of said equalizer, said first comparator providing an output signal corresponding to the sign of the difference between the gains at said two adjustable attenuators of said equalizer (, said first comparator providing an output signal corresponding to the sign of the difference between the gains at said two adjustable attenuators) a second comparator connected to the output of at least two other of the adjustable attenuators of said equalizer, said second comparator providing an output signal corresponding to the sign of the difference between the gains at said other two adjustable attenuators;

a clock means for providing a train of clock pulses;

a first and a second ADD/DELETE means receiving as an input said train of clock pulses;

first and second gate means connected to receive the output signal from said first and said second comparators, respectively;

a fixed rate alternating switch means for connecting the output of said second gate means alternately to the input of said first and said second ADD/DELETE means;

a first switch means for connecting the input of said first ADD/DELETE means in one position to the output of said first gate means and in the other position to said fixed rate alternating switch means;

first and second frequency divider means connected to receive the output from said first and said second ADD/DELETE means, respectively, the output of said first frequency divider means being a train of pulses that are proportional to the output carrier with the output of said second frequency divider being a train of pulses proportional to the output baud timing; and

two feedback means for connecting selected outputs from said second frequency divider means back to said first and said second gate means so as to control the time intervals at which said first and said second ADD/DELETE means add or delete pulses to the pulse trains entering said first and said second frequency dividers, thereby controlling the time intervals between consecutive incremenTal adjustments of the output carrier phase and the output baud timing.

2. In combination with an adjustable transversal eqaulizer having a (plural tapped delay line,) delay line with a plurality of taps, with adjustable attenuators respectively connected to (at least each) the plurality of taps on the delay line, with a preselected one of the plurality of taps being a main tap for a major signal component, and a summation circuit for combining the attenuated outputs of the adjustable attenuators into a single coordinated signal, the adjustable attenuators including a first pair of adjustable attenuators oppositely disposed about the attenuator connected to the main tap and a second pair of adjustable attenuators oppositely disposed from and mutually distinct from the first pair of adjustable attenuators, a carrier and timing recovery system comprising in combination:

a first comparing means for taking the difference between outputs from the first pair of adjustable attenuators (outputs located on either side of said main signal tap attenuator) and for providing a difference signal proportional to said difference;

a second comparing means for taking the difference between outputs from the second pair of (adjustable attenuator outputs located on either side of said first) adjustable attenuators and for providing a difference signal proportional to said difference;

a) first and second gate means having output terminals, said first and second gate means for receiving the difference (signal) signals from said first and second comparing means, respectively, and for respectively gating the received difference signals to (individual) said output terminals upon receipt of respective first and second control signals;

(a) first and (a) second pulse generating means being selectively responsive to said difference signals from said first and second comparing means for respectively generating first and second output trains of pulses, each of said first and second pulse generating means having an input and incrementally advancing or retarding the phase of (said trains) its associated output train of pulses (, the choice between advancing or retarding being controlled by) as a function of the sign of (said) the associated difference signal (from said first or said second comparing means, respectively) being applied thereto , the respective timing of (each advance/retardation) the advancing or retarding of the phases of said first and second output trains of pulses being selectively controlled by said first and said second gate means, (respectively,) the first output train of pulses (from said first pulse generating means) being (the system'"'"''"'"'s) output carrier pulses and the second output train of pulses (from said second pulse generating means) being (the system'"'"''"'"'s) output baud timing pulses, said (system output timing pulses being fed back through additional) second pulse generating means including frequency division (to said first and said second gate means as) means responsive to said output baud timing pulses for developing said first and second control signals;

alternating switch means having an output terminal for alternately connecting the output terminal of said second gate means to said output terminal of said alternating switch means and to the (inputs) input of said (first and) second pulse generating means; and

switch means interposed at the input of said first pulse generating means for connecting said input in one position to the output terminal of said first (gating) gate means and in the other position to the output terminal of said alternating switch means.

3. The invention according to claim 2 wherein said second pulse generating means is comprised of:

a clock means for generating a train of clock pulses at a frequency greater than that of the output (desired system) baud (frequency) timing pulses ;

ADD/DELETE means responsive to the (output) difference signal (of) from said second (gating) gate means for adding or deleting a pulse from said clock pulse train according to the sign of said (output) difference signal;

frequency (down counter) divider means for selectively dividing the frequency of the pulse train from said ADD/DELETE means (down to at least the desired baud frequency) to provide (gate timing) said baud timing pulses and said first and second control (pulse trains) signals ; and

first and second switch means for (connecting) applying the (provided gate timing) first and second control (pulse trains) signals to (the control terminal of) said first and second gate means, respectively.

4. The invention according to claim 2 wherein said first pulse generating means is comprised of:

a clock means for generating a train of clock pulses at a frequency greater than that of the (desired system'"'"''"'"'s) output baud (frequency) timing pulses ;

ADD/DELETE means responsive to the (output) difference signal (of) from said (first gating) switch means for adding or deleting a pulse from said clock pulse train according to the sign of said (output) difference signal; and

frequency (down counter) divider means for dividing the pulse train from said ADD/DELETE means down to at least the (desired baud) frequency of the baud timing pulses to provide the (system'"'"''"'"'s) output carrier pulses.

5. In combination with a high speed digital data receiver having a transversal equalizer with multiple tap gains and adjustable attenuators connected to each of the tap gains, the improvement comprising:

a first comparator connected to the output of at least two adjustable attenuators of said equalizer, said first comparator providing an output signal which is a function of the difference between the outputs of said two adjustable attenuators;

a second comparator connected to at least two other of the outputs of said adjustable attenuators, said second comparator providing an output signal corresponding to the sign of the difference between the outputs of the two other adjustable attenuators;

means for providing a periodic pulse train signal;

a first modulating means responsive to the signal from said first comparator for modulating the signal from said periodic pulse traiN means;

a second modulating means responsive to the signal from said second comparator for modulating the signal from said periodic pulse train means;

first and second frequency divider means (connected) coupled to (receive the output from) said first and said second modulating means, respectively, for respectively dividing the frequencies of the modulated periodic pulse train signals therefrom by preselected amounts ;

switch means interposed between the (output) outputs of said first and second (modulating means) comparators for controllably (connecting) applying the output signals of said first and second (modulating means) comparators to said first and second (comparator) modulating means ; and

feedback means for receiving (a signal) signals from said second frequency divider means and feeding said (signal) signals to said switch means to control the application of said output signals from said first and second comparators to said first and said second modulating means.