×

High speed transmission receiver utilizing fine receiver timing and carrier phase recovery

  • US RE28,638 E
  • Filed: 09/25/1974
  • Issued: 12/02/1975
  • Est. Priority Date: 03/18/1971
  • Status: Expired
First Claim
Patent Images

1. In combination with a high speed digital data receiver having a transversal equalizer with multiple adjustable attenuators, the improvement comprising:

  • a first comparator connected to the output of at least two adjustable attenuators of said equalizer, said first comparator providing an output signal corresponding to the sign of the difference between the gains at said two adjustable attenuators of said equalizer (, said first comparator providing an output signal corresponding to the sign of the difference between the gains at said two adjustable attenuators) a second comparator connected to the output of at least two other of the adjustable attenuators of said equalizer, said second comparator providing an output signal corresponding to the sign of the difference between the gains at said other two adjustable attenuators;

    a clock means for providing a train of clock pulses;

    a first and a second ADD/DELETE means receiving as an input said train of clock pulses;

    first and second gate means connected to receive the output signal from said first and said second comparators, respectively;

    a fixed rate alternating switch means for connecting the output of said second gate means alternately to the input of said first and said second ADD/DELETE means;

    a first switch means for connecting the input of said first ADD/DELETE means in one position to the output of said first gate means and in the other position to said fixed rate alternating switch means;

    first and second frequency divider means connected to receive the output from said first and said second ADD/DELETE means, respectively, the output of said first frequency divider means being a train of pulses that are proportional to the output carrier with the output of said second frequency divider being a train of pulses proportional to the output baud timing; and

    two feedback means for connecting selected outputs from said second frequency divider means back to said first and said second gate means so as to control the time intervals at which said first and said second ADD/DELETE means add or delete pulses to the pulse trains entering said first and said second frequency dividers, thereby controlling the time intervals between consecutive incremenTal adjustments of the output carrier phase and the output baud timing.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×