Digital computing system having auto-incrementing memory
First Claim
1. A plug-in library module for use in a digital computing system having a central processing unit which provides the address of a selected one of a plurality of sequentially accessed address location in said library module, provides a read memory signal and is responsive to processing information provided thereto in response to said address, and interface means including a plug-in type port for temporarily receiving the library module and for providing communication between the central processing unit and said library module, said library module comprising:
- memory means disposed within said library module, said memory means having processing information contained therein at sequentially accessed address locations, and outputting the processing information at each of said address locations in response to receiving the address thereof;
address counter means disposed within said library module for receiving and storing the address provided by said central processing unit, and providing said address stored therein to said memory means in response to the central processing means providing the read memory signal;
connector means disposed within said library module and connectable to the plug-in port of said interface means, said connector means connecting the address provided by said central processing unit to said address counter means, and connecting the processing information outputted by said memory means to said central processing unit; and
control means disposed within said library module and connected to said address counter means, said control means incrementing the address in said address counter means to the address of the next sequentially accessed address location in said memory means in response to said memory means outputting the processing information to said central processing unit in response to the address provided thereto by said address counter means, whereby the processing information contained in said next sequentially accessed address location will be provided by said memory means in response to a read memory .[.sianal.]. .Iadd.signal .Iaddend.provided by said central processing unit.
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Abstract
A digital computing system having an auto-incrementing memory subsystem includes one or more separate memories. Each memory in the memory subsystem has its own address counter which is automatically incremented to the next sequential address after each memory readout. In the case of plural memories, a page select enables memory readout only when a page designation portion of the address matches a unique page number associated with the memory. An automatic memory refresh is provided by a refresh address counter along with a refresh address incrementer in the case that a memory is a dynamic RAM. These features enable improved performance in the digital computing system by reducing the required CPU overhead for memory subsystem control.
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Citations
11 Claims
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1. A plug-in library module for use in a digital computing system having a central processing unit which provides the address of a selected one of a plurality of sequentially accessed address location in said library module, provides a read memory signal and is responsive to processing information provided thereto in response to said address, and interface means including a plug-in type port for temporarily receiving the library module and for providing communication between the central processing unit and said library module, said library module comprising:
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memory means disposed within said library module, said memory means having processing information contained therein at sequentially accessed address locations, and outputting the processing information at each of said address locations in response to receiving the address thereof; address counter means disposed within said library module for receiving and storing the address provided by said central processing unit, and providing said address stored therein to said memory means in response to the central processing means providing the read memory signal; connector means disposed within said library module and connectable to the plug-in port of said interface means, said connector means connecting the address provided by said central processing unit to said address counter means, and connecting the processing information outputted by said memory means to said central processing unit; and control means disposed within said library module and connected to said address counter means, said control means incrementing the address in said address counter means to the address of the next sequentially accessed address location in said memory means in response to said memory means outputting the processing information to said central processing unit in response to the address provided thereto by said address counter means, whereby the processing information contained in said next sequentially accessed address location will be provided by said memory means in response to a read memory .[.sianal.]. .Iadd.signal .Iaddend.provided by said central processing unit. - View Dependent Claims (2, 3)
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4. A digital computing system comprising:
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a plurality of memory means, each memory means having a unique predetermined page number associated therewith, each memory having processing information contained therein at sequentially accessed address locations, said memory means outputting the processing information at each of said address locations in response to receiving the address thereof; a central processing unit, responsive to said processing information, the central processing unit providing the address of a selected one of said sequentially accessed address locations and providing at least one read memory signal; a plurality of address counter means, each corresponding to one of the memory means, interposed between the central processing unit and the corresponding memory means, the address counter means each receiving and storing the address provided by the central processing unit, and providing said address stored therein to the corresponding memory means in response to the central processing unit providing the read memory signal; a plurality of control means, each corresponding to one of the address counter means, for incrementing the address in the corresponding address counter means to the address of the next sequentially accessed location in the corresponding memory means in response to the corresponding memory means outputting the processing information in response to the address provided thereto by the corresponding address counter means, whereby the processing information contained at said next sequentially accessed address location will be outputted by the corresponding memory means in response to a read memory signal provided by the central processing unit; a plurality of latch means, each interposed between a corresponding memory means and the central processing unit and responsive to the corresponding control means, each latch means further responsive to an enable signal, for receiving and storing the processing information outputted by the memory means and for providing said processing information to the central processing unit in response to the enable signal; and a plurality of page select means, each page select means corresponding to one of the memory means and responsive to the address stored in the corresponding address counter means for applying said enable signal to the corresponding latch means when a predetermined page designation portion of the address stored in the corresponding address counter means corresponds to the unique predetermined page number associated with the corresponding memory means. - View Dependent Claims (5)
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6. A digital computing system comprising:
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memory means of the dynamic random access type having processing information contained therein at sequentially accessed address locations, said memory means outputting the processing information at each of said address locations in response to receiving the address thereof; a central processing unit, responsive to said processing information, the central processing unit providing the address of a selected one of said sequentially accessed address locations and providing at least one read memory signal; an address counter means interposed between the central processing unit and the memory means, the address counter means receiving and storing the address provided by the central processing unit and providing said address in response to the central processing unit providing the read memory signal to the memory means; a control means, cooperating with the address counter means, for incrementing the address in the address counter means to the address of the next sequentially accessed address location in the memory means in response to the memory means outputting the processing information to the central processing means in response to the address provided thereto by the address counter means, whereby the processing information contained at said next sequentially accessed address location will be provided by said memory means in response to a subsequent read memory signal provided by the central processing unit; and a memory refresh means for periodically refreshing the processing information stored in the memory means. - View Dependent Claims (7, 8, 9, 10)
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11. A plug-in library module for use in a digital computing system having a central processing unit adapted to interact with a plurality of memory means each having a pre-assigned page number and a plurality of sequentially accessed address location, and wherein said central processing unit provides an address including both a page number corresponding to the pre-assigned page number of one of said plurality of memory means and the local address of a selected one of said plurality of sequentially accessed address locations, provides a memory access request including a read data signal, and is responsive to processing information provided thereto in response to said memory access request, and interface means including a plug-in type port for temporarily receiving said library module and for providing communication between the central processing unit and said library module, said library module comprising:
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one of said memory means disposed within said library module, said memory means having processing information contained therein at sequentially accessed address locations; first means for storing a page number provided by said central processing unit and for providing an enable signal when the stored page number corresponds to the pre-assigned page number of the memory means disposed within said library module, second means for storing the local address provided by said central processing unit and for providing said local address to the memory means disposed within said library module, connector means disposed within said library module and connectable to the plug-in port of said interface means, said connector means connecting the address provided by said central processing unit to said first and second storage means, and connecting the processing information outputted by said memory means to said central processing unit; and control means responsive to the receipt from said central processing unit of a memory access request including a read data signal and to said enable signal for outputting the processing information at the memory location corresponding to the local address provided to said memory means and for incrementing the local address in said second storage means to the address of the next sequentially accessed location in said memory means, said control means being further operative to maintain the local address located in said second storage means in an unaltered state in the absence of a memory access request, whereby the processing information contained in said next sequentially accessed address location will be provided by said memory means in response to another memory access request including a read data signal..Iaddend.
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Specification