Numeric data processor

• US RE33,629 E
• Filed: 06/01/1990
• Issued: 07/02/1991
• Est. Priority Date: 02/13/1980
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Palmer, John F., Ravenel, Bruce W., Nave, Rafi
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US07/461,538
• Time in Patent Office: 396 Days
• Field of Search: 364/748, 364/745, 364/737, 364/736, 364/200
• US Class Current: 708/510
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/4991 Overflow or underflow
• CPC Class Codes: G06F 7/49947 Rounding
• CPC Class Codes: G06F 7/49957 Implementation of IEEE-754 Standard
• CPC Class Codes: G06F 7/49963 Rounding to nearest G06F7/49957 takes precedence
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers, long or short integer words or BCD data upon which it must operate. As a result the circuit has a greater reliability, range and precision than ever previously achieved without entailing additional circuit complexity. Reliability is further enhanced by a systematic three bit rounding field, and by including means for detecting every error or exception condition with an optional expected response provided thereto by hardware. As a result of such organization, an unexpected increase of capacity is achieved wherein transcendental functions can be computed totally in hardware, and whereby mixed mode arithmetic can be implemented without difficulty. The numeric processor also includes a programmable shifter capable of arbitrary numbers of bit and byte shifts in a single clock cycle, as well as an arithmetic unit capable of implementing multiplication, division, modulo reduction and square roots directly in hardware.

Claims

1. An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising:

first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data format;

a fraction and exponent bus coupled to said first means;

a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus;

an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus; and

means for rounding said numeric information in a selected one of a plurality of modes,

wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to a numeric quantity, said sticky bit being the Or-function of all right shifted bits from said numeric quantity beyond the bit location of said guard and round bits. .[.2. An improvement in a numeric data processor for performing calculations on numeric quantities comprising;

first means for detecting and indicating numeric exceptions during computational operation and handling of said numeric quantities wherein said exceptions include signed zeros and infinity;

second means for selectively masking a response to said numeric exceptions;

third means for selectively providing a specific response to each said exception when said exception is masked, said third means being coupled to said second and first means;

means for rounding said numeric quantities in a selected one of a plurality of modes,

wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to said numeric quantity, said sticky bit being the exclusive-or function of all right shifted bits from one of said numeric quantities..]. .[.3. An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of;

converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats;

storing said converted data format in file format within a stack of registers;

selectively coupling said file format numeric quantities to a fraction and exponent bus;

selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon; and

rounding said numeric quantities in one of a plurality of modes by means for rounding,

wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to a numeric quantity, said sticky bit being the exclusive-or function of all right shifted bits from said numeric quantity beyond the bit location of said guard and round

2. bits..]. .[.4. An improvement in a method for calculating numeric quantities comprising the steps of:

detecting every numeric exceptions during computational operations in a numeric processor;

indicating the nature of said exceptions detected in a status register;

generating a response in hardware within said numeric processor specific to the indicated exception without generating an interrupt signal, including the exception of operations employing and resulting in signed zeros and infinity; and

3. selectively masking said generated response..]. 5. An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising:

first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data formats;

a fraction and exponent bus coupled to said first means;

a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus;

an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus;

means for rounding said numeric information in a selected one of a plurality of modes; and

means for performing exact arithmetic including a P flag register and PM mask register, wherein said P flag register is set if rounding occurs within said means for rounding and an interrupt is generated by an interrupt means, and wherein if said PM mask register is set, execution continues without interrupt generation with a rounded result generated by said means for rounding,

whereby reliability of calculation is increased. .[.6. An improvement in a numeric data processor for performing calculations on mumeric quantities comprising;

first means for detecting and indicating numeric exceptions during computational operation and handling of said numeric quantities wherein said exceptions included signed zeros and infinity;

second means for selectively masking a response to said numeric exceptions;

third means for selectively providing a specific response to each said exception when said exception is masked, said third means being coupled to said second and first means;

means for rounding said numeric quantities in a selected one of a plurality of modes; and

means for performing exact arithmetic including a P flag register and PM mask register, wherein said P flag register is set if rounding occurs within said means for rounding and an interrupt is generated by an interrupt means, and wherein if said PM mask register is set, execution continues without interrupt generation with a rounded result generated by said means for rounding,

whereby every exception during numeric processing is detected and indicated and if masked, will be provided with a response so that calculation may

4. proceed in a reliable manner..]. 7. An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of:

converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats;

storing said converted data format in file format within a stack of registers;

selectively coupling said file format numeric quantities to afraction and exponent bus;

selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon;

rounding said numeric quantities in one of a plurality of modes by a means for rounding;

selectively setting a P flag register if rounding occurs; and

generating an interrupt if a PM mask register is not set, otherwise

5. generating a rounded result. 8. An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising:

first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data formats;

a fraction and exponent bus coupled to said first means;

a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus;

an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus;

second means for detecting and indicating numeric exceptions during computational operation and handling of said information;

third means for selectively masking a response to said numeric exceptions; and

fourth means for selectively providing a specific response in hardware and without the generations of an interrupt signal to each said exception when said exception is masked, said fourth means being coupled to said second and third means,

whereby every exception during numeric processing is detected and indicated, and if masked, will be provided with a response so that calculation may proceed in a reliable manner. .[.9. An improvement in a numeric data processor for performing calculations on numeric quantities comprising;

first means for detecting and indicating numeric exceptions during computational operation and handling of said information wherein said exceptions include signed zeros and infinity;

second means for selectively masking a response to said numeric exceptions; and

third means for selectively providing a specific response in hardware and without generating an interrupt signal, said third means being coupled to said second and first means,

whereby every exception during numeric processing is detected and indicated and if masked, will be provided with a response so that calculation may

6. proceed in a reliable manner..]. 10. An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of:

converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats;

storing said converted data format in file format within a stack of registers;

selectively coupling said file format numeric quantities to a fraction and exponent bus;

selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon;

reconverting a file format numeric quantity in said stack of registers by said conversion means into a selected one of said plurality of data formats;

detecting and indicating numeric exceptions during said steps of converting, reconverting, performing arithmetic operations in an error detection means; and

selectively providing a specific response to each said exception in hardware without generating an interrupt signal when said exception is masked by an error handling means.