Digital level sensing probe system

• US RE34,731 E
• Filed: 12/22/1992
• Issued: 09/20/1994
• Est. Priority Date: 05/29/1991
• Status: Expired due to Term

• Current Assignee: Dilli Technology, Inc.
• Original Assignee: Lee/Maatuk Engineering Incorporated
• Inventors: Lee, Calvin S., Tousson, Eliahou
• Primary Examiner(s): Cuchlinski, Jr., William A.
• Assistant Examiner(s): GUTIERREZ, DIEGO F
• Application Number:
  US07/995,203
• Time in Patent Office: 637 Days
• Field of Search: 73/304 C, 324/665
• US Class Current: 73/304.00C
• CPC Class Codes: G01F 23/265 for discrete levels
• CPC Class Codes: G01F 23/266 measuring circuits therefor
• CPC Class Codes: G01F 23/268 mounting arrangements of probes

Abstract

Digital level sensing probe system including digital probe constructed of two (2) concentric cylinders, forming a set of discrete, cylindrical capacitors that use the substance whose level is to be measured as a dielectric material. The set of capacitors is arranged along the axis of measurement where each capacitor represents a discrete level increment. Each capacitor is assigned a unique time slot in a switching sequence. The first level capacitor is used as a reference to which all other capacitors are sequentially compared. In the switching sequence, an AC signal is applied across each capacitor and compared with the inverted signal which is applied across the first level capacitor. A logic "1" results when the substance is present and a logic "0" when the substance is absent. The logic is decoded and converted to display the appropriate quantity of substance measured.

Claims

1. Digital fluid level sensing probe system comprising digital probe fluid level sensing means constructed of a set of .Iadd.isolated .Iaddend.capacitors arranged along an axis of measurement where each capacitor represent a discrete level increment in dielectric material fluid to be measured, switching sequence means wherein each capacitor is assigned a unique time slot for sequential comparison .Iadd.to a .Iaddend.reference .[.to a first level capacitor.]., means for applying an AC signal in switching sequence across .[.each capacitor above the first level capacitor.]. .Iadd.succeeding capacitors.Iaddend., means for .[.applying an inverted AC signal across the first level capacitor.]. .Iadd.establishing a reference signal.Iaddend.for comparison with each of said AC signals applied in switching sequence, including means for discriminating between .Iadd.the .Iaddend.respective .Iadd.compared .Iaddend.signals to provide a logic "1" when fluid is present and a logic "0" when fluid is absent, or vice versa, and means for decoding and converting said logic to display the appropriate quantity of fluid measured in increments corresponding to said .[.discrete.]. .Iadd.isolated .Iaddend.capacitors.

2. System of claim 1 wherein each capacitor includes flexible printed circuits with capacitor electrodes and circuit connections etched onto a flexible printed circuit medium.

3. System of claim 2 wherein said flexible printed circuit capacitors are attached to rigid concentric cylinders.

4. System of claim 2 wherein each capacitor is formed by aligning the etched circuits in concentricity along the longitudinal axis of the probe.

5. System of claim 3 wherein said rigid cylinders are positively detented to accurately align the printed circuits and therefore the capacitor electrodes.

6. System of claim 1 wherein said capacitors are constructed as an integral part of rigid cylinders.

7. System of claim 1 wherein said Capacitors have no common electrodes or interconnections.

8. System of claim 1 wherein all capacitors in the set .Iadd.to which said AC signal is applied in switching sequence .Iaddend.are grounded except the .[.first level capacitor and the.]. single capacitor .[.being monitored.]. .Iadd.having the AC signal applied.Iaddend..

9. System of claim 1 including reset means whereby each capacitor in the set is repeatedly recompared while being .[.monitored.]. .Iadd.compared .Iaddend.in its assigned unique time slot.

10. System of claim 9 .[.including reset means.]. wherein the time slots when each capacitor is compared to the .[.first level capacitor.]. .Iadd.reference .Iaddend.are reset .Iadd.by said reset means .Iaddend.each time a signal that fluid is absent occurs.

11. System of claim 10 including means for grounding all .[.other.]. capacitors .[.during the monitoring.]. .Iadd.in the set to which said AC signal is applied in switching sequence except the single capacitor having the AC signal applied. .Iaddend.

12. System of claim 1 including means wherein the capacitors are sequentially monitored in a wraparound mode.

13. System of claim 12 including means for applying a signal V across each capacitor in sequence wherein the output from each monitored sequence is presented sequentially.

14. System of claim 13 including means for reading the output directly in Binary-Coded-Decimal format.

15. System of claim 1 including an integrated EPROM or equivalent nonvolatile storage device for container profile.

16. System of claim 15 including a software algorithm for each container shape written into the nonvolatile storage device.

17. System of claim 16 wherein said nonvolatile storage device includes memory for volumetric data.

18. System of claim 1 including linear operational amplifiers as current-to-voltage converters.

19. System of claim 18 wherein said operational amplifiers include means for amplifying the output data at the same time.

20. System of claim 1 including means for providing said set of capacitors in a uniform set of individual capacitors having capacitances of less than one picofarad each.