Multiplex interface for a communication controller

• US RE34,896 E
• Filed: 05/29/1991
• Issued: 04/04/1995
• Est. Priority Date: 12/04/1985
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Feraud, Jacques M. C., Calvignac, Jean L. J., Munier, Jean-Marie L.
• Primary Examiner(s): MARCELO, MELVIN C
• Application Number:
  US08/052,189
• Time in Patent Office: 1,406 Days
• Field of Search: 370/84, 370/85.1, 370/95.1, 370/99, 370/100.1, 370/105.1, 370/105.2, 370/105.4, 370/110.1
• US Class Current: 370/359
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 12/525 involving a stored program control

Abstract

A multiplex interface for interconnecting the line scanning means (1) of a communication controller to user lines via transmit and receive synchronous multiplex links. Both data and control bits are exchanged in synchronous frames wherein at least two slots are assigned to each user line, the structure of the two slots is identical for all types of user lines and includes an n-bit data slot having a variable number x of valid bits depending upon the line speed of the user line assigned to the data slot and indicated by a variable delimiter pattern comprising a first delimiting bit set at a first binary value (1) adjacent to the data bits and (n--x--1) bits set at the second binary value (0) adjacent to said first delimiting bit, and an n-bit control slot having a first bit used as a global validation bit in case the data slot comprises n valid bits (x═n), this bit being set at the first binary value (1) when the data slot comprises n valid bits and at the second binary value (0) if it comprises less than n valid bits, and the n--following bits are used for exchanging control information.

Claims

1. A multiplex interface (17,3) for interconnecting a line scanning means (1) of a communication controller, in order to exchange data and control bits, to user lines attached to the communication controller, characterized in that said multiplex interface comprises:

transmit and receive synchronous multiplex links (3-T,3-F) connecting the line scanning means to the users through multiplexing means (17), the data and control bits being exchanged on the transmit and receive multiplex links in synchronous frames wherein at least two slots are assigned to each user, the structure of the two slots being identical for all types of users and comprising;

an n-bit data slot which includes a variable number x of valid bits depending upon the speed of the user information carrying medium.Iadd., .Iaddend.line or multiplex .[.).]. link.[.).]., assigned to the data slot, said number being indicated by a variable delimitation pattern comprising a first delimiting bit set at a first binary value (1) adjacent to the data bits and (n-x-1) bits set at the second binary value (0) adjacent to said first delimiting bit; and

an n-bit control slot wherein a first bit is used as global validation bits in case the data slot comprises n valid bits (x═

n),.]. .Iadd.including at least one global validation bit, .Iaddend.this bit being set at the first binary value (1) when the data slot comprises n valid bits and at the second binary value (0) if it comprises less than n valid bits, and the n-1 other bits being used for exchanging control information;

said multiplexing means including;

frame synchronization detecting means (30,

     32) responsive to the bit stream on at least one multiplex link (3-T or 3-R) for generating therefrom a frame synchronization signal delimiting the succession of slots in the successive frames and a bit clock signal at the bit rate on the multiplex link;

slot time allocating means (54,

     50) responsive to the bit clock signal and to the frame synchronization signal for generating selection signals (66) which are active to indicate the two slot periods assigned to the users;

at least one receiving means, each one of the receiving means (FIG.

     8) receiving the data and control bits from one attached user at the speed of the user information carrying medium and arranging them into entities having the structure of the data and control bit slots to be sent on the receive link (3-R), said entities being sent to the line scanning means when the selection signal relative to the user is active;

at least one transmitting means (FIG.

     10), each one of the transmitting means receiving the bits from the transmit link arranged in data and control slots and responsive to the selection signal relative to the user for causing the valid data bits and the control bits to be sent to the user at the user information carrying medium speed.

2. Multiplex interface according to claim 1, characterized in that each receiving means comprises:

data receiving means (68, 72,

     70) which receives the user line data at the line bit rate,

means (80) for storing a variable delimitation pattern comprising a first bit at the first binary value adjacent to n-1 bits at the second binary value,

deserializing means (78) connected to the data receiving means for assembling the data bits received from the user line,

data serializing means (76) comprising a n-bit shift register the content of which is shifted at the link bit clock signal rate,

control means (74) for causing the deserializing means content to be loaded into the data serializing means and the variable delimitation pattern to be transferred into the deserializing means when the selection signal relative to the line user becomes active and for shifting the deserializing means content at the line bit rate,

gating means (84) responsive to the line selection signal and to the link bit clock signal for generating an output signal which is applied to the serializing means for causing the content of the serializing means to be shifted at the link clock signal rate except during the first link clock pulse of the link clock signal following the time when the line selection signal becomes active.

3. Multiplex interface according to claim 2, characterized in that the receiving means comprise:

control bit receiving means (102, 104,

     110) receiving the control bits from the user line which are associated to the data bits,

control bit serializing means (108), receiving the control bits when the line selection signal becomes active and the content of which is shifted under control of the output signal from the gating means, said control bit serializing means connected to the output of the data serializing means and providing on its output the serial data and control bits to be sent to the receive link when the selection signal is active.

4. Multiplex interface according to claim 3 characterized in that the control slot comprises positions to exchange:

the global validation bit (G)

a transmit request bit (TR) which is set at an active level in the control slot to be sent to the line scaning means when all data bits in a slot have been transmitted, to cause a new data bit slot to be sent on the transmit link,

at least two internal control bits (N, I) which are used for transmitting control information to the line scanning means,

at least one external control bits (E) which are used to receive or send control bits to the user lines in synchronism with the data bits which are received or sent.

5. Multiplex interface according to claim 4, characterized in that the deserializing means of the receiving means is a (n+1) stage shift register, the (n+1)th stage of which is taken as the global validation bit of the control slot.

6. Multiplex interface according to .Iadd.claim 4 or 5 .Iaddend..[.any one of claim 1 to 5,.]. characterized in that the transmitting means comprises at least one deserializing means (206) which receive serially the data and control bits from the line scanning means and which provides the assembled data and control bits on a data output bus (207) and a control output bus (209) and for each user line:

data register means (212) which is loaded with the data bits and the global validation bit from the output busses of the deserializing means at the end of the active period of the line selection signal,

serializing means comprising a n+1 shift register which is loaded with the data register means content and the content of which is then shifted at the user line speed to provide the valid data bits contained in the data slot to the user line, means (232, 224,

     230) for detecting that all valid data bits have been sent for causing the serializing means to be loaded with the data register content,

means (240,

     242) responsive to the means for detecting that all valid bits have been sent for setting the transmit request bit (TR) on the control slot to be sent on the receive link (3-R).

7. Multiplex interface according to claim 6, characterized in that the means for detecting that all valid data bits have been sent comprise:

a comparator (220) which compares the content of the serializing means with .[.the.]. .Iadd.a .Iaddend.variable delimitation pattern indicating that a data slot contains no valid data bit,

first logic control means (224, 236,

     216) responsive to the comparator output signal for preventing the serializing means to be shifted when the comparator indicates an equality,

second logic control means (230) responsive to the comparator output signal for causing the content of the data register means to be loaded into the deserializing means when the comparator indicates an equality.

8. Multiplex interface according to claim 7, characterized in that it comprises latching means (240, 242) responsive to the output signal of the comparator for setting the transmit request .[.control.]. bit (TR) in the control slot on the receive link when the comparator indicates an equality.

9. Multiplex interface according to claim 1, characterized in that only one receiving means receives the data and control bits from a multiplex user link in a plurality of user channels and comprises:

deserializing means (612) to which the bits from the multiplex user link are provided and shifted at the multiplex user link speed, the frame synchronization detecting means (614) being responsive to the deserializing means content for generating the frame synchronization signal delimiting the slots in the successive frames on the receive multiplex link,

data slot serializing means (622) comprising a n-bit shift register which is loaded at each channel per-iod with the deserializing means content under control of the selection signals provided by the slot time allocating means (616,

     618) and the content of which is shifted at the link bit clock rate, said data slot serializing means providing at its output, the data bits to be sent in the data slots on the receive multiplex link,

means (624,

     627) responsive to the deserializing means content for recognizing the channels containing external control information and providing an active output signal when said channels are recognized,

control slot serializing means (632) comprising a n-bit shift register, the content of which is shifted at the clock bit rate,

gating means (630) for loading the deserializing means into the control slot serializing means when the means recognizing the channels containing control information generate an active output signal.

10. Multiplex interface according to claim 9 characterized in that only one transmitting means performs the transmission of the data and control bits from the multiplex transmit link to the multiplex user link and comprises:

deserializing means (700) to which the data and control bits from the multiplex transmit link are provided and in which they are shifted at the multiplex link bit clock rate,

serializing means (706) comprising a n-bit shift register which is loaded at each channel period with the deserializing means content under control of the selection signals provided by the slot time allocation means (708,

     710) and providing on its output the bits to be sent on the multiplex user link,

means (716, 714, 728,

     726) recognizing the channels in which control bits have to be sent to prevent the data bit content of the deserializing means from being loaded into the serializing means and causing the control bits to be loaded into the serializing means to be sent to the .[.multiple.]. .Iadd.multiplex .Iaddend.user link. .Iadd.

11. A line interface circuit suitable for exchanging information bits between a communication line operating at one of a number of different clock speeds and a miltiplexer associated with a communication controller via a multiplex frame having associated therewith a frame synchronization signal and a bit clock, said multiplex frame including a plurality of slots at least one of which is assigned to the said line interface circuit and includes n+1 bits, said n+1 bits being partitioned between a variable number of valid information bits x which range from 0-n and padding bits y according to the equation v=n-x and a delimiter bit having a value different than said padding bits and interposed between the information and padding bits, comprising:

first means responsive to the frame synchronization signal and the multiplexer bit clock for identifying at least one slot in the multiplex frame assigned to the line interface circuit;

second means operating at the communication line clock speed for generating a transmit clock signal corresponding thereto;

third means responsive to the multiplex frame, the multiplex bit clock and the first means for storing the content of the slot assigned to the line interface circuit;

fourth means for storing n+1 bits and providing a first control signal when the storage includes n padding bits and one delimiter bit; and

,

fifth means responsive to the transmit clock signal and the first control signal for loading the contents of the third means into the fourth means, controlling the application of the transmit clock signal to the fourth means and for generating a request signal to be sent to the multiplexer whereby information bits in the fourth means are supplied to the communication line and additional information bits are made available to the line interface circuit via the multiplex frame after the contents of the third means are loaded into the fourth means. .Iaddend. .Iadd.12. A line interface circuit suitable for exchanging information bits between a communication line operating at one of a number of different clock speeds and a multiplexer associated with a communication controller via a multiplex frame having associated therewith a frame synchronization signal and a bit clock, said multiplex frame including a plurality of slots at least one of which is assigned to the said line interface circuit and includes n+1 bits, and said n+1 bits being partitioned between a variable number of valid information bits x which range from 0-n and padding bits y according to the equation y=n-x and a deliminiter bit having a value different than said padding bits and interposed between the information and padding bits, comprising;

first means reponsive to the frame synchronization signal and the multiplexer bit clock for identifying at least one slot in the multiplex frame assigned to the line interface circuit;

receiver/driver means connected to said communication line for receiving and providing a clock signal corresponding to the selected clock speed of the information bits received from the connected communication line and for providing information bits to said communication line;

second means responsive to the multiplex frame, the multiplex bit clock and the first means for storing the content of a slot assigned to the line interface circuit;

third means for storing n+1 bits and providing a first control signal when the storage includes n padding bits and one delimiter bit; and

,

fourth means responsive to the clock signal from the receiver/driver means and the first control signal for loading the contents of the second means into the third means, controlling the application of the said clock signal to the third means and for generating a request signal to be sent to the multiplexer whereby information bits in the third means are supplied to the receiver/driver means for transmission over the communication line and additional information bits are made available to the line interface circuit via the multiplex frame after the contents of the second means are

12. loaded into the third means. .Iaddend. .Iadd.13. A line interface circuit suitable for exchanging information bits between a communication line operating at one of a number of different clock speeds and a multiplexer associated with a communication controller via a multiplex frame having associated therewith a frame synchronization signal and a bit clock, said multiplex frame including a plurality of slots at least one of which is assigned to the said line interface circuit and includes n+1 bits, said n+1 bits being partitioned between a variable number of valid information bits x which range from 0-n and padding bits y according to the equation y=n-x and a delimiter bit having a value different than said padding bits and interposed between the information and padding bits, comprising:

first means responsive to the frame synchronization signal and the multiplexer bit clock for providing a first signal identifying at least one slot in the multiplex frame assigned to the line interface control circuit;

second means responsive to the information bits from the communication line for formatting at least n+1 bits within a predetermined time period corresponding to the frame synchronization signal period, said n+1 bits including x information bits, where x is equal to or less than n, provided by the communcation line in said predetermined time period, a delimiter bit and n-x padding bits; and

third means connected to said second means for receiving the formatted at least n+1 bits under control of the said frame synchronization signal and for transmitting the said at least n+1 bits serially under control of the multiplex bit clock and the first signal provided by the said first means.

13. Iaddend. .Iadd.14. A line interface circuit suitable for exchanging information bits between a communication line operating at one of a number of different clock speeds and a multiplexer associated with a communcation controller via a multiplex frame having associated therewith a frame synchronization signal and a bit clock, said multiplex frame including a plurality of slots at least one of which is assigned to the said line interface circuit and includes n+1 bits, said n+1 bits being partitioned between a variable number of valid information bits x which range from 0-n and padding bits y according the equation y=n-x and a delimiter bit having a value different than said padding bits and interposed between the information and padding bits, comprising:

first means responsive to the frame synchronization signal and the multiplexer bit clock for providing a signal identifying at least one slot in the multiplex frame assigned to the line interface circuit;

receiver conntected to said communication line for receiving and providing information bits and a clock signal corresponding to the selected clock speed of the information bits received from the connected communication line;

second means responsive to the receiver means for formatting at least n+1 bits within a predetermined time period corresponding to the frame synthronization signal period, said n+1 bits including x information bits, where x is equal to or less than n, provided by the receiver means in said predetermined time period, a delimiter bit and n-x padding bits; and

,

third means connected to said second means for receiving the formatted at least n+1 bits under control of the said frame synchronization and for transmitting the said at least n+1 bits serially under control of the multiplex bit clock and the first signal provided by the said first means.