Textured metallic compression bonding

• US RE35,119 E
• Filed: 01/14/1992
• Issued: 12/12/1995
• Est. Priority Date: 07/21/1988
• Status: Expired due to Term

• Current Assignee: AT&T Corporation (AT&T, Inc.)
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Fulton, Theodore A., Blonder, Greg E.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/820,730
• Time in Patent Office: 1,428 Days
• Field of Search: 357/68, 357/74, 357/75, 357/79, 257/739, 257/785, 361/400, 361/403, 361/760, 361/767
• US Class Current: 257/739
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13019 at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/8103 Reshaping the bump connector in the bonding apparatus, e.g. flattening the bump connector
• CPC Class Codes: H01L 2224/81205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/81224 using a laser
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/8183 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/98 Methods for disconnecting semiconductor or solid-state bodies
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon career, and depositing the gold on the silicon dioxide layer.

Claims

1. In combination

(a) a semiconductor integrated circuit chip having an integrated circuit connected to a plurality of metallic chip pads located on a major surface of the chip;

(b) a carrier upon which are located metallic wiring interconnections having metallic carrier pads that are .Iadd.compression .Iaddend.bonded to the chip pads, each of .Iadd.either .Iaddend.the carrier pads.[.,.]. .Iadd.or the .Iaddend.chip pads, .[.or.]. .Iadd.but not .Iaddend.both.Iadd., .Iaddend.having at least a portion thereof that is textured .Iadd.prior to bonding .Iaddend.with indentations whose depths are.[., or protrusions whose heights are,.]. of the order of one micrometer.

2. The combination described in claim 1 in which each chip pad has a portion that is separated from the major surface of the chip by a portion of a localized layer of an insulating material, and in which each carder pad has a portion, underlying a complementary portion of the layer of insulating material, that is indented in the vertical direction and is smooth, the insulating material having relatively little or no adhesive tendency with respect to the chip pad.

3. The combination of claim 2 in which the carrier comprises a silicon wafer and in which the pads are bonded such that a tensile force of about 1 kg per mm² or more of pad area is required to pull them apart.

4. The combination of claim 3 in which the silicon wafer has a plurality of V-grooves at each of such portions thereof underlying the carrier pads.

5. The combination of claim 2 in which surfaces of the chip pads are essentially gold.

6. The combination of claim 5 in which surfaces of the carrier pads are essentially gold and in which the chip pads are nondestructively detachable from the carrier pads by means of a mechanical pulling apart.

7. The combination of claim 1 in which the chip carrier comprises a silicon wafer which is textured at the portions thereof .[.underlying.]. .Iadd.bonded to .Iaddend.the carrier pads.

8. The combination of claim 7 in which the silicon wafer has a plurality of V-grooves at each of such portions thereof .[.underlying.]. .Iadd.bonded to .Iaddend.the carrier pads.

9. The combination of claim 1 in which areas of the carrier pads to be bonded to chip pads are essentially gold and in which the chip pads are nondestructively detachable from the carrier pads by means of a mechanical pulling apart.

11. The combination of claim 1 in which surfaces of the chip pads are essentially gold.

12. The combination of claim 1 in which the indentations .[.or protrusions.]. have widths, as measured at the tops .[.of the protrusions.]. or bottoms of the indentations, of about 1 micrometer or less. .Iadd.13. In combination:

a first body having a first metallic layer located contiguous with a first surface of the first body; and

a second body having a second metallic layer being compression bonded to the second metallic layer, either the first metallic layer or the second metallic layer, but not both the first and second metallic layers, having at least a portion thereof that is textured prior to bonding with indentations whose depths are of the order of one micrometer or less. .Iaddend. .Iadd.14. The combination of claim 13 in which the second body comprises a wafer and in which the first and second metallic layers are bonded such that a tensile force of about 1 kg per mm² or more of metallic area is required to pull them apart. .Iaddend. .Iadd.15. The combination of claim 13 in which a surface of the first metallic layer is essentially gold. .Iaddend. .Iadd.16. The combination of claim 15 in which a surface of the second metallic layer is essentially gold and in which the first metallic layer is nondestructively detachable from the second metallic layer by means of a mechanical pulling apart. .Iaddend. .Iadd.17. The combination of claim 13 in which the second body comprises a wafer which is textured at the portion thereof bonded to the second metallic layer. .Iaddend. .Iadd.18. The combination of 17 in which the wafer has a plurality of V-grooves at the portion thereof bonded to the second metallic layer. .Iaddend. .Iadd.19. The combination of claim 13 in which areas of the second metallic layer that are bonded to the first metallic layer are essentially gold, and in which the first metallic layer is nondestructively detachable from the second metallic layer by means of a

10. The combination of claim .[.10.]. .Iadd.9 .Iaddend.in which the surfaces of the chip pads are essentially .[.gold.]. .Iadd.gold.Iaddend..

13. mechanical pulling apart. .Iaddend. .Iadd.20. The combination of claim 19 in which the surface of the first metallic layer is essentially gold. .Iaddend. .Iadd.21. The combination of claim 13 in which a surface of the

14. first metallic layer is essentially gold. .Iaddend. .Iadd.22. The combination of claim 13 in which the indentations have widths, as measured at the tops or at the bottoms of the indentations, of about 1 micrometer or less. .Iaddend.