Time delayed digital video system using concurrent recording and playback

• US RE36,801 E
• Filed: 04/18/1996
• Issued: 08/01/2000
• Est. Priority Date: 10/29/1992
• Status: Expired due to Term

• Current Assignee: Bernice C. Logan, Motorola Mobility LLC (Lenovo Group Ltd.)
• Original Assignee: James Logan
• Inventors: Goessling, Daniel, Logan, James
• Primary Examiner(s): Miller, John W.
• Application Number:
  US08/634,618
• Time in Patent Office: 1,566 Days
• Field of Search: 348/1, 348/5, 348/7, 348/10, 348/559, 348/560, 348/725, 348/571, 348/722, 348/714, 369/60, 386/1, 386/33, 386/34, 386/35, 386/40, 386/46, 386/68, 386/109, 386/124, 360/13
• US Class Current: 348/571
• CPC Class Codes: H04N 21/4147 PVR [Personal Video Recorder] H04N5/76 takes precedence ; arrangements for broadcast with accumulation-type receivers H04H20/40
• CPC Class Codes: H04N 5/44 Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/4448 for frame-grabbing
• CPC Class Codes: H04N 5/76 Television signal recording

Abstract

A broadcast recording and playback device employing a "circular buffer" which constantly records one or more incoming audio or video program signals and a microprocessor for accessing the memory to read a playback signal from the circular buffer to display programming material delayed from its receipt by a selectable delay interval. The circular buffer is implemented by a digital memory. Subsystem comprising the combination of a semiconductor RAM memory and a disk memory operated under the control of a microprocessor such that incoming signals are constantly recorded as received while, at the same time, delayed signals are being read from the memory subsystem at a different memory location selected by a microprocessor to provide a user-selected time delay. A plurality of input signal processors provides one or more programming signals to the memory subsystem in compressed digital form and a separate output signal processor converts the compressed digital information read from the memory into a form suitable for display. The audio/video buffer system operates under the control of a microprocessor which accepts commands from a remote command device or a connected host computer.

Claims

1. In combination,

means for generating a substantially continuous sequence of .[.a.]. digital .[.television.]. input signal values .Iadd.representing an incoming audio or video program signal.Iaddend.,

a source of control commands,

a .[.television.]. .Iadd.program .Iaddend.signal utilization device, and

a variable delay circular storage buffer .Iadd.for storing those of said digital input signal values which were received during the immediately preceding time intervals of predetermined duration, said circular storage buffer .Iaddend.having an input port connected to receive said digital .[.television.]. input signal values and an output port connected to supply a delayed replica of said input signal values to said utilization device following a variable delay interval, the duration of said interval being selectable in response to said control commands, said circular storage buffer comprising, in combination:

an addressable digital memory,

a programmed processor,

memory access means for continuously writing said sequence of digital .[.television.]. input signal values into said addressable digital memory.[.,.]. at a sequence of .Iadd.continually advancing .Iaddend.writing addresses established by said processor .Iadd.to write over the oldest of said input signal values recorded in said digital memory as said sequence of writing addresses are advanced so that said digital input signal values received during said immediately preceding time interval of predetermined duration are stored in said addressable digital memory, .Iaddend.and for concurrently reproducing and supplying to said output port an output sequence of previously written ones of signal values read from said addressable digital memory at a sequence of different reading addresses established by said processor, and

means for supplying said output sequence to said output port,

wherein said programmed processor includes means responsive to said control commands for varying the relative locations of said reading and writing addresses to selectively alter said variable delay interval.

2. The combination set forth in claim 1 wherein said means for generating said input signal values comprises, in combination,

means for receiving an analog .[.television.]. program signal,

an analog-to-digital converter for translating said program signal into

a first sequence of digital values, and

data compression means for translating said first sequence of digital

values into more compact form for storage in said addressable memory,

wherein said combination further comprises data decompression means connected between said output port and said utilization device.

3. The combination as set forth in claim 2 wherein said compression means is responsive to said processor means for varying the compression ratio at which said first sequence of digital values is translated into more compact form.

4. The combination as defined in claim 1 .Iadd.wherein said program signal is a television signal and .Iaddend.wherein one of said control commands is a pause command and wherein said programmed processor further includes means responsive to said pause command for maintaining said reading addresses to repeatedly send a portion of the television signal stored in said memory to said output port.

5. The combination as defined in claim 4 wherein one of said control commands is a playback speed command and wherein said programmed processor further includes means responsive to said playback speed command for altering the rate at which said reading addresses are changed.

6. The combination as defined in claim 4 wherein one of said control commands is a reverse command and wherein said programmed processor further includes means responsive to said playback speed command for altering said reading addresses in a reverse order from the sequence of writing addresses used to store said television input signal to thereby provide a reverse motion television signal to said output port.

7. The combination as defined in claim 1 .Iadd.wherein said program signal is a television signal and .Iaddend.wherein one of said control commands include a replay selection command and wherein said programmed processor further includes means for selectively accessing data at a plurality of different frame addresses stored in said digital memory to form data representing a mosaic of reduced size images, each of said images representing data at a corresponding one of said frame addresses, and wherein said programmed processor further includes means responsive to said replay selection command for setting said reading address to a selected one of said frame addresses identified by said replay selection command.

8. The combination as set forth in claim 7 wherein said compression means includes means responsive to said processor means for varying the compression ratio at which said first sequence of digital values is translated into more compact form. .Iadd.

9. The combination set forth in claim 1 wherein said variable delay circular storage buffer stores one or more incoming signals and wherein said means for concurrently reproducing and supplying to said output port an output sequence of previously written ones of signal values includes means responsive to a user command for selecting a particular one of said one or more incoming signals for reproduction. .Iaddend..Iadd.

10. The combination as set forth in claim 9 further comprising an input unit composed of one or more simultaneously operating signal processors each connected to a source of programming signals for supplying said one or more incoming signals to said storage buffer. .Iaddend.