Flash memory array and decoding architecture

• US RE37,419 E1
• Filed: 10/29/1999
• Issued: 10/23/2001
• Est. Priority Date: 06/05/1997
• Status: Expired due to Term

• Current Assignee: Secure Axcess LLC (Prism Technologies Group, Inc.)
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Hsu, Fu-Change, Tsao, Hsing-Ya, Lee, Peter W.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/430,060
• Time in Patent Office: 725 Days
• Field of Search: 365/185.11, 365/185.05, 365/185.29, 365/185.33, 438/258
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/115 Electrically programmable read-only memories; Multistep manufacturing processes therefor

Abstract

A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and a verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing. Several different approaches are presented for the layout of source segment control lines and transistors as well as the word lines.

Claims

1. A flash memory array, which is divided into a plurality of memory segments, comprising:

a plurality of flash memory cells being arranged in a plurality of rows and a plurality of columns, each of the memory segments having at least one column and each of said flash memory cells having a control gate, a floating gate, a drain and a source, said floating gate being formed in a first polysilicon layer and said control gate being formed in a second polysilicon layer;

a plurality of odd word lines formed in said second polysilicon layer, each odd word line connecting the control gates of all the flash memory cells in a same odd row;

a plurality of even word lines formed in said second polysilicon layer, each even word line connecting the control gates of all the flash memory cells in a same even row and forming a word line pair with a neighboring odd word line;

a plurality of bit lines each connecting the drains of all the flash memory cells in a same column;

a plurality of source lines each being associated with a word line pair; and

a plurality of segmented source lines in each memory segment, each of said segmented source lines being formed by wiring together the sources of all the memory cells in a word line pair within a memory segment and then connected to the source line associated with the word line pair through at least one source segment control transistor having a gate coupled to a source segment control line of the memory segment, said source segment control line and said source segment control transistor being formed in a third polysilicon layer.

2. The flash memory array according to claim 1, said third polysilicon layer being a polysilicon layer different from said second polysilicon layer.

3. The flash memory array according to claim 1, said third polysilicon layer being a polysilicon layer below said second polysilicon layer.

4. The flash memory array according to claim 1, said third polysilicon layer being a polysilicon layer above said second polysilicon layer.

5. A flash memory array, which is divided into a plurality of memory segments, comprising;

a plurality of flash memory bells being arranged in a plurality of rows and a plurality of columns, each of the memory segments having at least one column and each of said flash memory cells having a control gate, a floating gate, a drain and a source, said floating gate being formed in a first polysilicon layer and said control gate being formed in a second polysilicon layer;

a plurality of odd word lines, each odd word line comprising;

a plurality of odd word line segments formed in said second polysilicon layer, each odd word line segment connecting the control gates of all the flash memory cells in a same odd row in a memory segment; and

a plurality of word line segment connectors formed in a first conductive layer for connecting said odd word line segments in a same odd row and forming an odd word line;

a plurality of even word lines, each even word line forming a word line pair with a neighboring odd word line and comprising;

a plurality of even word line segments formed in said second polysilicon layer, each even word line segment connecting the control gates of all the flash memory cells in a same even row in a memory segment; and

a plurality of word line segment connectors formed in a second conductive layer for connecting said even word line segments in a same even row and forming an even word line;

a plurality of bit lines each connecting the drains of all the flash memory cells in a same column;

a plurality of source lines each being associated with a word line pair; and

a plurality of segmented source lines in each memory segment, each of said segmented source lines being formed by wiring together the sources of all the memory cells in a word line pair within a memory segment and then connected to the source line associated with the word line pair through at lest one source segment control transistor having a gate coupled to a source segment control line of the memory segment, said source segment control line and said source segment control transistor being formed in said second polysilicon layer.

6. The flash memory array according to claim 5, wherein said first conductive layer is a polysilicon or metal layer different from said second polysilicon layer.

7. The flash memory array according to claim 5, wherein said second conductive layer is a polysilicon or metal layer different from said second polysilicon layer.

8. The flash memory array according to claim 5, wherein said first and second conductive layers are a same polysilicon or metal layer which is different from said second polysilicon layer.

9. The flash memory array according to claim 5, wherein said word line segment connectors for connecting the odd word line segments in a same odd row are in series and form a connector line in said first conductive layer.

10. The flash memory array according to claim 5, wherein said word line segment connectors for connecting the even word line segments in a same even row are in series and form a connector line is said second conductive layer.

11. A flash memory comprising:

12. The flash memory of claim 11, further comprising:

13. The flash memory of claim 11, wherein:

14. The flash memory of claim 12, wherein: