Dual-node capacitor coupled MOSFET for improving ESD performance
First Claim
1. An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising:
- a MOSFET device having a source, a drain, a gate and a bulk;
a capacitor connected the gate of said MOSFET and a pad terminal;
a first resistor connected between the gate and the bulk of said MOSFET; and
a second resistor connected between the bulk and a power bus.
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Abstract
A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.
19 Citations
57 Claims
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1. An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising:
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a MOSFET device having a source, a drain, a gate and a bulk;
a capacitor connected the gate of said MOSFET and a pad terminal;
a first resistor connected between the gate and the bulk of said MOSFET; and
a second resistor connected between the bulk and a power bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An ESD protection circuit for lowering the trigger voltage and improving the turn-on consistency of a MOSFET device, comprising:
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a MOSFET device having a source, a drain, a gate and a bulk;
a capacitor connected between the gate of said MOSFET and a first power bus;
a first resistor connected between the gate and the bulk of said MOSFET; and
second resistor connected between the bulk and a second power bus. - View Dependent Claims (18, 19, 20, 21)
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22. An ESD protection structure, comprising:
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a MOSFET device comprising a source, a drain, a gate and a body;
a capacitor coupled between said gate and said drain;
a first resistor coupled between said gate and said body; and
a second resistor coupled between said body and said source. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. An ESD protection circuit for an integrated circuit, comprising:
a MOS transistor having a source node, a drain node, a gate node and a base node, wherein said gate node is coupled to a first node through a capacitor and is coupled to a second node through a first resistor, wherein said base node is coupled to the first node through said capacitor and is coupled to the second node through said first resistor, and wherein said first node is subject to electrostatic-discharge stress during an ESD event. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. An ESD protection circuit, comprising:
a MOS transistor having a source node, a drain node, a gate node, and a base node, wherein said gate node is coupled to a first node through a first impedance and is coupled to a second node through a second impedance, wherein said base node is coupled to the first node through said first impedance and is coupled to the second node through said second impedance, and wherein said first node is subject to electrostatic-discharge stress during an ESD event. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
Specification