DC-to-DC controller having a multi-phase synchronous buck regulator

• US RE38,371 E1
• Filed: 12/19/2001
• Issued: 12/30/2003
• Est. Priority Date: 06/15/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dinh, James S.
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US10/021,350
• Time in Patent Office: 741 Days
• Field of Search: 323/282, 323/351, 363/62, 307/64, 307/66
• US Class Current: 323/282
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

A DC-to-DC regulator that includes a multi-phase synchronous buck regulator having a pulse width modulator to generate a plurality of switching signals, a plurality of drivers, each coupled to receive one of the switching signals, and a plurality of switching voltage converters, each coupled to receive an output from one of the drivers and an input voltage, wherein the outputs of the switching voltage converters are combined to form an output voltage. The multi-phase synchronous buck regulator can be implemented on a motherboard, such as on an interposer board or directly on a PU chip.

Claims

1. A DC-to-DC regulator, comprising:

a multi-phase synchronous buck regulator including;

a pulse width modulator to generate a plurality of switching signals, at least one of said switching signals being out-of-phase with respect to other ones of said switching signal signals,

a plurality of drivers, each coupled to receive one of said switching signals, and

a plurality of switching voltage converters, each coupled to receive an output from one of said drivers and an input voltage, wherein the outputs of said switching voltage converters are combined to form an output voltage, and

wherein said multi-phase synchronous buck regulator is implemented on a motherboard.

2. The DC-to-DC regulator of claim 1, further comprising a droop circuit to add a droop voltage to said output voltage.

3. The DC-to-DC regulator of claim 2, wherein said multi-phase synchronous buck regulator is coupled to receive a plurality of input voltages, and wherein said multi-phase synchronous buck regulator further comprises a sequence timing control circuit to allow proper operation of said multi-phase synchronous buck regulator regardless of the sequencing of said input voltages.

4. The DC-to-DC regulator of claim 1, wherein said multi-phase synchronous buck regulator further comprises an over-voltage protection circuit.

5. The DC-to-DC regulator of claim 1, wherein said multi-phase synchronous buck regulator is implemented on a central processing unit chip.

6. The DC-to-DC regulator of claim 5, wherein said pulse width modulator comprises a programmable, multi-phase high performance PWM controller.

7. The DC-to-DC regulator of claim 6, wherein each of said drivers comprises a high speed synchronous power MOSFET smart driver.

8. The DC-to-DC regulator of claim 7, wherein each of said switching voltage converters includes a plurality of switching MOSFETs, and an output inductor.

9. The DC-to-DC regulator of claim 1, wherein said multi-phase synchronous buck regulator is implemented on an interposer.

10. The DC-to-DC regulator of claim 9, wherein said pulse width modulator comprises a PWM controller.

11. The DC-to-DC regulator of claim 1,

wherein the switching signal from one phase to a next phase are separated by 90° .

13. The DC-to-DC regulator of claim 11, wherein the switching signals from one phase to a next phase are separated by 90°

.

12. A DC-to-DC regulator, comprising:

a plurality of multi-phase synchronous buck regulator modules, wherein each of said modules includes;

a pulse width modulator to generate a plurality of switching signals, at least one of said switching signals being out-of-phase with respect to other ones of said switching signals.

a plurality of drivers, each coupled to receive one of said switching signals.

a plurality of switching voltage converters, each coupled to receive an output from one of said drivers and an input voltage, wherein the outputs of said switching voltage converters are combined to form an output voltage, and

a current sharing circuit to insure that the current load is shared amongst said plurality of multi-phase synchronous buck regulator modules,

and wherein said multi-phase synchronous buck regulator modules are implementedon a motherboard.

14. A system comprising a DC-to-DC regulator comprising:

a multi-phase synchronous buck regulator including;

a pulse width modulator to generate a plurality of switching signals, at least one of said switching signals being out-of-phase with respect to other ones of said switching signals,

a plurality of drivers, each coupled to receive one of said switching signals, and

a plurality of switching voltage converters, each coupled to receive an output from one of said drivers and an input voltage, wherein the outputs of said switching voltage converters are combined to form an output voltage, and

wherein said multi-phase synchronous buck regulator is implemented on a motherboard.

15. The system of claim 14, further comprising a droop circuit to add a droop voltage to said output voltage.

16. The system of claim 15, wherein said multi-phase synchronous buck regulator is coupled to receive a plurality of input voltages, and wherein said multi-phase synchronous buck regulator further comprises a sequence timing control circuit to allow proper operation of said multi-phase synchronous buck regulator regardless of the sequencing of said input voltages.

17. The system of claim 14, wherein said multi-phase synchronous buck regulator further comprises an over-voltage protection circuit.

18. The system of claim 14, wherein said multi-phase synchronous buck regulator is implemented on a central processing unit chip.

19. The system of claim 18, wherein said pulse width modulator comprises a programmable, multi-phase, high performance PWM controller.

20. The system of claim 19, wherein each of said drivers comprises a high speed synchronous power MOSFET smart driver.

21. The system of claim 20, wherein each of said switching voltage converters includes a plurality of switching MOSFETs, and an output inductor.

22. The system of claim 14, wherein said multi-phase synchronous buck regulator is implemented on an interposer.

23. The system of claim 22, wherein said pulse width modulator comprises a PWM controller.

24. The system of claim 14,

wherein the switching signals from one phase to a next phase are separated by 90° .

25. A system comprising a DC-to-DC regulator comprising:

a plurality of multi-phase synchronous buck regulator modules, wherein each of said modules includes;

a pulse width modulator to generate a plurality of switching signals, at least one of said switching signals being out-of-phase with respect to other ones of said switching signals,

a plurality of drivers, each coupled to receive one of said switching signals,

a plurality of switching voltage converters, each coupled to receive an output from one of said drivers and an input voltage, wherein the outputs of said switching voltage converters are combined to form an output voltage, and

a current sharing circuit to insure that the current load is shared amongst said plurality of multi-phase synchronous buck regulator modules,

and wherein said multi-phase synchronous buck regulator modules are implemented on a motherboard.

26. The system of claim 25,

wherein the switching signals from one phase to a next phase are separated by 90° .

27. A DC-to-DC regulator, comprising:

a multi-phase synchronous buck regulator including;

a pulse width modulator to generate a plurality of switching signals, at least one of said switching signals being out-of-phase with respect to other ones of said switching signals,

28. The DC-to-DC regulator of claim 27, wherein said multi-phase synchronous buck regulator is implemented on an interposer.

29. The DC-to-DC regulator of claim 28, wherein said multi-phase synchronous buck regulator is coupled to receive a plurality of input voltages, and wherein said multi-phase synchronous buck regulator further comprises a sequence timing control circuit to allow proper operation of said multi-phase synchronous buck regulator regardless of the sequencing of said input voltages.

30. The DC-to-DC regulator of claim 27, further comprising a droop circuit to add a droop voltage to said output voltage.

31. A system comprising a DC-to-DC regulator comprising:

a plurality of multi-phase synchronous buck regulator modules, wherein each of said modules includes;

a pulse width modulator to generate a plurality of switching signals, at least one of said switching signals being out-of-phase with respect to other ones of said switching signals,

32. The system of claim 31, wherein said multi-phase synchronous buck regulator modules are implemented on an interposer.

33. A DC-to-DC regulator, comprising:

a plurality of multi-phase synchronous buck regulator modules, wherein each of said modules includes;

a pulse width modulator to generate a plurality of switching signals, at least one of said switching signals being out-of-phase with respect to other ones of said switching signals,

34. The DC-to-DC regulator of claim 33, wherein said multi-phase synchronous buck regulator modules are implemented on an interposer.

35. A system comprising a DC-to-DC regulator comprising:

a multi-phase synchronous buck regulator including;

a pulse width modulator to generate a plurality of switching signals, at least one of said switching signals being out-of-phase with respect to other ones of said switching signals,

36. The system of claim 35, wherein said multi-phase synchronous buck regulator is coupled to receive a plurality of input voltages, and wherein said multi-phase synchronous buck regulator further comprises a sequence timing control circuit to allow proper operation of said multi-phase synchronous buck regulator regardless of the sequencing of said input voltages.

37. The system of claim 35, wherein said multi-phase synchronous buck regulator is implemented on an interposer.

38. The system of claim 35, wherein said multi-phase synchronous buck regulator is implemented on a central processing unit chip.

39. The system of claim 35, further comprising a droop circuit to add a droop voltage to said output voltage.