Insulated gate semiconductor device and method of manufacturing the same

• US RE38,953 E1
• Filed: 05/01/2003
• Issued: 01/31/2006
• Est. Priority Date: 04/01/1996
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US10/426,700
• Time in Patent Office: 1,006 Days
• Field of Search: 257/341, 257/331, 257/139, 257/146, 257/147
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The RBSOA of a device is improved. A gate electrode (10) is linked to a p base layer (4) which is formed in a cell region (CR), and a p semiconductor layer (13) is formed to surround the cell region (CR). An emitter electrode (11) is connected to a top surface of a side diffusion region (SD) of the p semiconductor layer (13) and to a top surface of a margin region (MR) which is adjacent to the side diffusion region (SD), through a contact hole (CH). Further, in these regions, an n⁺ emitter layer (5) is not formed. Most of avalanche holes (H) which are created in the vicinity of the side diffusion region (SD) when a high voltage is applied pass through the side diffusion region (SD), while some of the avalanche holes (H) pass through the margin region (MR) and are then ejected to the emitter electrode (11). Since there is no n⁺ emitter layer (5) in these paths, a flow of the holes (H) does not conduct a parasitic bipolar transistor. As a result of this, the RBSOA is improved.

Claims

1. An insulated gate semiconductor device comprising a semiconductor base defining a top major surface and a bottom major surface, wherein

said semiconductor base includes:

a first semiconductor layer of a first conductivity type being exposed to said top major surface;

a second semiconductor layer of a second conductivity type being formed in a portion of said top major surface within said first semiconductor layer;

a third semiconductor layer of the second conductivity type formed in a portion of said top major surface within said first semiconductor layer by selectively diffusing an impurity, said third semiconductor layer being deeper than said second semiconductor layer, said third semiconductor layer being linked to said second semiconductor layer, said third semiconductor layer surrounding said second semiconductor layer; and

a fourth semiconductor layer of the first conductivity type being selectively formed in a portion of said top major surface within said second semiconductor layer,

in said semiconductor base, a trench is formed which is open in said top major surface, which penetrates said fourth and said second semiconductor layers and which reaches said first semiconductor layer,

said device further comprises;

a gate insulation film covering an inner wall of said trench;

a gate electrode which is buried within said trench, with said gate insulation film located between said gate electrode and said semiconductor base;

a gate wire line which is disposed on said top major surface through an insulation film so as to extend along said third semiconductor layer, said gate wire line being electrically connected to said gate electrode;

a first major electrode which is disposed on said top major surface, said first major electrode being electrically connected to said second and said fourth semiconductor layers; and

a second major electrode which is disposed on said bottom major surface, said second major electrode being electrically connected to said bottom major surface,

said first major electrode is also electrically connected to a side diffusion region which is adjacent to said second semiconductor layer within said third semiconductor layer and has a convexly sloping diffusion structure on a side of said side diffusion region which is adjacent to said second semiconductor layer, and

said fourth semiconductor layer is not formed within said third semiconductor layer including said side diffusion region,

said trench extends between opposed portions of said third semiconductor layer which face each other across said second semiconductor layer and extend parallel to each other, said trench extending across said side diffusion region in each of said opposed portions of said third semiconductor layer, said trench extending to a portion of said third semiconductor layer located outside said side diffusion region and immediately under said gate wire line,

said gate insulation film is not formed immediately on said gate electrode which fills in a longitudinal end portion of said trench located within said portion of said third semiconductor layer immediately under said gate wire line, and

said gate electrode filling in said longitudinal end portion is electrically connected to said gate wire line.

2. The insulated gate semiconductor device of claim 1, wherein said first major electrode is also electrically connected to a margin region which is defined as a region within a certain distance from said side diffusion region in said second semiconductor layer, and

said fourth semiconductor layer is not formed within said margin region, either.

3. The insulated gate semiconductor device of claim 2, wherein said certain distance is approximately equal to or smaller than 50 μ

m.

4. The insulated gate semi conductor device of claim 1, wherein in said trench is divided into a plurality of unit trenches which are arranged parallel to each other and equidistant from each other.

5. The insulated gate semiconductor device of claim 1 wherein, referring to said trench as a first trench, to said gate insulation film as a first gate insulation film, and to said gate electrode as a first gate electrode, said semiconductor device further comprises:

a second trench formed in said semiconductor base and which is open in said top major surface and is located in said third semiconductor layer in parallel to said first trench;

a second gate insulation film which ensures electric insulation, said second gate insulation film covering an inner wall of said second trench; and

a second data electrode which is buried within said second trench, with said second gate insulation film located between said second gate electrode and said semiconductor base,

wherein said gate wire line is connected to said second gate electrode.

6. The insulated gate semiconductor device of claim 1, wherein an edge portion of said trench along the longitudinal direction of said trench extends into said third semiconductor layer.

7. The insulated gate semiconductor device of claim 1, wherein said semiconductor base further includes a fifth semiconductor layer which is selectively formed in a connection portion of said second and said third semiconductor layers with said first major electrode, said fifth semiconductor layer having a higher impurity concentration than those of said second and said third semiconductor layers.

8. The insulated gate semiconductor device of claim 1, wherein said fourth semiconductor layer is exposed to regions which are located between said plurality of unit trenches within said top major surface, so as to be in a ladder-like configuration which is adjacent to said plurality of unit trenches.

9. The insulated gate semiconductor device of claim 1, wherein said semiconductor base further includes a sixth semiconductor layer of the second conductivity type, and said sixth semiconductor layer is jointed to said first semiconductor layer and exposed to said bottom major surface.

10. The insulated gate semiconductor device of claim 9, wherein said first semiconductor layer includes a seventh semiconductor layer of the first conductivity type in a junction portion with said sixth semiconductor layer, and said seventh semiconductor layer has a higher impurity concentration than that of a remaining portion of said first semiconductor layer.

11. The insulated gate semiconductor device of claim 1,

wherein said portion of said third semiconductor layer immediately under said gate wire line is at a greater depth than said trench.