Run to run control process for controlling critical dimensions
DC CAFCFirst Claim
1. A method of fabricating an integrated circuit comprising:
- pattern, exposure, and develop a photoresist layer on a wafer in a photolithography process that forms a plurality of structures on the integrated circuit including a gate;
measuring a DICD critical dimension of the gate following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation;
etching the wafer including etching of the gate;
measuring a FICD critical dimension of the gate following etching of the wafer in a Final Inspection Critical Dimensions (FICD) operation;
feeding forward the DICD critical dimension to a process model;
feeding back the FICD critical dimension to the process model; and
controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity.
1 Assignment
Litigations
0 Petitions
Accused Products
Abstract
It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist each time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power as a manipulated variable. A run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specification. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis. The run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification. The run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable.
-
Citations
104 Claims
-
1. A method of fabricating an integrated circuit comprising:
-
pattern, exposure, and develop a photoresist layer on a wafer in a photolithography process that forms a plurality of structures on the integrated circuit including a gate;
measuring a DICD critical dimension of the gate following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation;
etching the wafer including etching of the gate;
measuring a FICD critical dimension of the gate following etching of the wafer in a Final Inspection Critical Dimensions (FICD) operation;
feeding forward the DICD critical dimension to a process model;
feeding back the FICD critical dimension to the process model; and
controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A method of fabricating an integrated circuit comprising:
-
pattern, expose, and develop a photoresist layer on a plurality of wafers in a photolithography process that forms a plurality of structures on the integrated circuit including a gate;
measuring a DICD critical dimension of the gate in a pilot subset of the plurality of wafers following developing of the photoresist layer in a Develop Inspection Critical Dimensions (DICD) operation;
etching wafers of the plurality of wafers remaining after removal of the pilot subset, the etching including etching of the gate;
measuring a FICD critical dimension of the gate following etching of the plurality of wafers remaining after removal of the pilot subset in a Final Inspection Critical Dimensions (FICD) operation;
feeding forward the DICD critical dimension to a process model;
feeding back the FICD critical dimension to the process model; and
controlling a photoresist deposit and etch process recipe parameter in the process model according to the DICD critical dimension and the FICD critical dimension of the gate to improve critical dimension uniformity. - View Dependent Claims (19, 20)
-
-
21. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer;
performing a photoresist etching process on the patterned layer of photoresist;
etching the gate electrode material layer to define at least one gate electrode in said gate electrode material layer;
measuring a critical dimension of said at least one gate electrode; and
controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one gate electrode. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer comprised of polysilicon formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer;
performing a photoresist etching process on the patterned layer of photoresist;
etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of gate electrodes comprised of polysilicon;
measuring a critical dimension of a plurality of said gate electrodes; and
controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of gate electrodes. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40)
-
-
41. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer comprised of polysilicon formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer;
performing a photoresist etching process on the patterned layer of photoresist;
etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of gate electrodes comprised of polysilicon;
measuring a critical dimension of a plurality of said gate electrodes;
feeding back the measured critical dimensions of the plurality of gate electrodes to a process model; and
controlling a duration of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of gate electrodes. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48)
-
-
49. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer;
performing a photoresist etching process on the patterned layer of photoresist;
etching the gate electrode material layer to define at least one patterned feature in said gate electrode material layer;
measuring a critical dimension of said at least one patterned feature; and
controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon said measured critical dimension and a target critical dimension for said at least one patterned feature. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62)
-
-
63. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer;
performing a photoresist etching process on the patterned layer of photoresist;
etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features;
measuring a critical dimension of a plurality of said patterned features; and
controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features. - View Dependent Claims (64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74)
-
-
75. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer;
performing a photoresist etching process on the patterned layer of photoresist;
etching the gate electrode material layer using the etched patterned layer of photoresist as a mask to define a plurality of patterned features;
measuring a critical dimension of a plurality of said patterned features;
feeding back the measured critical dimensions of the plurality of patterned features to a process model; and
controlling at least one parameter of a photoresist etching process to be performed on a patterned layer of photoresist formed above at least one subsequently provided wafer based upon a comparison between said measured critical dimensions and a target critical dimension for said plurality of patterned features. - View Dependent Claims (76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86)
-
-
87. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer, said patterned layer of photoresist having a plurality of features formed therein;
measuring a critical dimension of at least one of said features in said patterned layer of photoresist prior to performing a photoresist etching process on said patterned layer of photoresist; and
controlling a duration of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist. - View Dependent Claims (88, 89, 90)
-
-
91. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer, said layer of photoresist having a plurality of features formed therein;
measuring a critical dimension of at least one of said features in said patterned layer of photoresist prior to performing a photoresist etching process on said patterned layer of photoresist;
determining a duration of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist; and
performing said photoresist etch process for said determined duration on a patterned layer of photoresist formed above at least one subsequently processed wafer. - View Dependent Claims (92, 93, 94)
-
-
95. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer, said patterned layer of photoresist having a plurality of features formed therein;
measuring a critical dimension of at least one of said features in said patterned layer of photoresist prior to performing a photoresist etching process on said patterned layer of photoresist; and
controlling at least one parameter of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist. - View Dependent Claims (96, 97, 98, 99)
-
-
100. A method of fabricating an integrated circuit device, comprising:
-
providing a wafer having a gate electrode material layer formed thereabove;
forming a patterned layer of photoresist above the gate electrode material layer, said layer of photoresist having a plurality of features formed therein;
measuring a critical dimension of at least one of said features in said patterned layer of photoresist prior to performing a photoresist etching process on said patterned layer of photoresist;
determining at least one parameter of said photoresist etching process based upon at least said measured critical dimension of said at least one feature in said patterned layer of photoresist; and
performing said photoresist etch process for said determined duration on a patterned layer of photoresist formed above at least one subsequently process wafer. - View Dependent Claims (101, 102, 103, 104)
-
Specification