Probe card having groups of probe needles in a probing test apparatus for testing semiconductor integrated circuits

• US RE41,016 E1
• Filed: 01/18/2005
• Issued: 12/01/2009
• Est. Priority Date: 09/27/1995
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Momohara, Tomomi
• Primary Examiner(s): Nguyen; Vinh P
• Application Number:
  US10/952,594
• Time in Patent Office: 1,778 Days
• Field of Search: 324754-762, 324/765, 324/760, 438 14- 17, 439/482, 439/824
• US Class Current: 324/754.07
• CPC Class Codes: N/A

Abstract

A probe card which can help to enhance the productivity of semiconductor integrated circuits manufacturing and to reduce the manufacturing cost thereof, and a method of probe-testing semiconductor integrated circuits by using the probe card. The probe card is designed to test semiconductor integrated circuits formed on a semiconductor wafer and arranged in rows and columns. It has groups of probe needles provided to contact semiconductor integrated circuits arranged in two columns and at least two rows. The card receives a test signal from a test device and supplies the test signal simultaneously to these semiconductor integrated circuits arranged in two columns and at least tow rows, through the groups of probe needles. It receives response signals simultaneously from the semiconductor integrated circuits through the groups of probe needles and then supplies the response signals to the tester.

Claims

1. A probe card for use in probing test of semiconductor integrated circuits arranged on a semiconductor wafer in rows and columns, comprising:

a card substrate;

groups of probe needles, said groups arranged on said card substrate in two columns and at least two rows, to contact connection terminals of semiconductor integrated circuits which are arranged in two columns and at least two rows, and

groups of signal lines, each group of signal lines provided for one group of probe needles, each signal line provided for supplying a test signal from a tester to one probe needle and a response signal from the probe needle to the tester,

wherein a test signal supplied from said tester is supplied from said probe needles to the semiconductor integrated circuits arranged in two columns and at least two rows at the same time through said groups of probe needles, and response signals generated by the semiconductor integrated circuits arranged in two columns and at least two rows are simultaneously supplied to the tester through said groups of probe needles.

2. The probe card according to claim 1, wherein said card substrate has a rectangular through hole having first and second long sides, the probe needles of the groups extend through the rectangular through hole, the probe needles of some groups are arranged along the first long side of the rectangular hole to contact the connection terminals of the semiconductor integrated circuits arranged in the first column, and the probe needles of the other groups are arranged along the second long side of the rectangular through hole to contact the connection terminals of the semiconductor integrated circuits arranged in the first column.

3. The probe card according to claim 1, wherein connection terminals of the semiconductor integrated circuits comprise a plurality of pads which are arranged in at least two columns.

4. The probe card according to claim 2, which further comprises groups of contacts exposed on a surface of said card substrate, to be connected to the tester, and groups of wires connecting the groups of probe contacts to the groups of probe needles;

and in which said probe substrate consists of first and second halves divided along a longitudinal axis of said rectangular hole, the wires connected to the probe needles to contact the connection terminals of the semiconductor integrated circuits arranged in the first column and the probe contacts connected to these wires are provided on the first half of said probe substrate, and the wires connected to the probe needles to contact the connection terminals of the semiconductor integrated circuits arranged in the second column and the probe contacts connected to these wires are provided on the second half of said probe substrate.

5. The probe card according to claim 4, wherein said probe substrate comprises a plurality of layers, said wires are divided into groups in accordance with types of signals and types of powers, and the groups of wires, thus formed, are provided on the layers, respectively.

6. A method of testing semiconductor integrated circuit chips, the method comprising:

coupling each of a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and each of the plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;

preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;

coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;

concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;

concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;

concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;

concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester; and

concurrently comparing electrical characteristics of the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.

7. The method according to claim 6, wherein the external terminals are centrally disposed within the integrated circuit chips.

8. The method according to claim 6, wherein the integrated circuit chips include a memory array.

9. The method according to claim 6, wherein the independent test signals and the independent power supply are supplied from the independent external tester to the probe needles by way of a plurality of wiring lines on internal layers of the probe card.

10. The method according to claim 6, wherein the independent test signals and the independent power supply are supplied from the independent external tester to the probe needles by way of the probe contact terminals and the mechanical wirings on different internal layers of the probe card.

11. A method of testing semiconductor integrated circuit chips, the method comprising:

coupling a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;

preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;

coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips, the plurality of probe needles being arranged on the probe card in at least two columns and at least two rows, the plurality of probe needles corresponding to those of the plurality of external terminals;

concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;

concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;

concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;

concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester; and

concurrently comparing the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.

12. A method of testing semiconductor integrated circuit chips, the method comprising:

coupling each of a plurality of probe contact terminals on at least one probe card to an independent external tester, the probe card having a plurality of probe needles and each of the plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;

preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;

coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;

concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;

concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;

concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;

concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester; and

concurrently comparing electrical characteristics of the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.

13. The method according to claim 12, wherein the independent test signals and the independent power supply are supplied from the independent external tester to the probe needles by way of a plurality of wiring lines on internal layers of the probe card.

14. The method according to claim 12, wherein the independent test signals and the independent power supply are supplied from the independent external tester to the probe needles by way of the probe contact terminals and the mechanical wirings on different internal layers of the probe card.

15. The method according to claim 12, further comprising:

preparing at least one test station; and

attaching a plurality of probe cards to the at least one test station.

16. A method of testing semiconductor integrated circuit chips, the method comprising:

coupling a plurality of probe contact terminals on at least one probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;

preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;

coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips, the plurality of probe needles being arranged on the probe card in at least two columns and at least two rows, the plurality of probe needles corresponding to those of the plurality of external terminals;

concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;

concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;

concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;

concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester; and

concurrently comparing the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.

17. A method of testing semiconductor integrated circuit formed in a semiconductor wafer, the method comprising:

coupling a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;

preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;

coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;

concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;

concurrently supplying a plurality of test signals and power supply voltages through the plurality of probe needles on the probe card to the external terminals on each of the plurality of semiconductor integrated circuit chips in at least two columns and at least two rows from the independent external tester;

concurrently receiving independent data output signals from each of the plurality of semiconductor integrated circuit chips in at least two columns and at least two rows by the independent external tester through the external terminals, the probe needles and the probe contacts; and

concurrently comparing electrical characteristics of the plurality of independent data output signals of each of plurality of semiconductor integrated circuit chips by the independent external tester.