Frequency-stabilized transceiver configuration
First Claim
Patent Images
1. A transceiver configuration for a communication terminal, comprising:
- an A/D converter outputting a first digital data signal;
a D/A converter;
a controllable oscillator circuit connected to said A/D converter and to said D/A converter, said controllable oscillator circuit having a reference oscillator with an oscillating crystal as a resonator and outputs a sampling clock received by said A/D converter and said D/A converter;
a digital data processing circuit connected to said A/D converter and to said D/A converter and receives the first digital data signal output by said A/D converter and processes it further and outputs a second digital data signal to said D/A converter;
said A/D converter, said D/A converter, said data processing circuit and said controllable oscillator circuit, apart from said oscillating crystal of said reference oscillator, being constructed as a monolithically integrated circuit so that of said controllable oscillator circuit, only said oscillating crystal is implemented as an external component; and
a frequency section being at least one of a radio-frequency section and an intermediate-frequency section connected to said A/D converter, to said D/A converter and to said controllable oscillator circuit, said frequency section having a frequency converter stage operating with a beat frequency derived from said controllable oscillator circuit.
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Abstract
A transceiver configuration has an integrated circuit (IC) with an A/D and/or D/A converter, a VCO with a reference oscillator, which provides a sampling clock for the A/D and/or D/A converter, and a digital data processing circuit. The IC is connected to a radio-frequency section, the frequency converter stage of which is operated with a beat frequency derived from the controllable oscillator frequency foz. A capacitive resonant element of the reference oscillator is disposed outside of the IC.
34 Citations
29 Claims
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1. A transceiver configuration for a communication terminal, comprising:
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an A/D converter outputting a first digital data signal;
a D/A converter;
a controllable oscillator circuit connected to said A/D converter and to said D/A converter, said controllable oscillator circuit having a reference oscillator with an oscillating crystal as a resonator and outputs a sampling clock received by said A/D converter and said D/A converter;
a digital data processing circuit connected to said A/D converter and to said D/A converter and receives the first digital data signal output by said A/D converter and processes it further and outputs a second digital data signal to said D/A converter;
said A/D converter, said D/A converter, said data processing circuit and said controllable oscillator circuit, apart from said oscillating crystal of said reference oscillator, being constructed as a monolithically integrated circuit so that of said controllable oscillator circuit, only said oscillating crystal is implemented as an external component; and
a frequency section being at least one of a radio-frequency section and an intermediate-frequency section connected to said A/D converter, to said D/A converter and to said controllable oscillator circuit, said frequency section having a frequency converter stage operating with a beat frequency derived from said controllable oscillator circuit. - View Dependent Claims (2, 3, 4)
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5. A transceiver configuration, comprising:
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an A/D converter;
a D/A converter;
an oscillator circuit configured to provide a sampling clock that is received by the A/D converter and the D/A converter;
a digital data processing circuit that receives a first digital data signal from the A/D converter and provides a second digital data signal to the D/A converter; and
a frequency section coupled to the A/D converter and the D/A converter, wherein the frequency section comprises a frequency converter stage that operates with a beat frequency derived from the sampling clock. - View Dependent Claims (6, 7)
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8. A transceiver, comprising:
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an A/D converter;
a D/A converter;
an oscillator circuit configured to provide a clock signal to the A/D converter and the D/A converter, wherein the clock signal is corrected by comparing a control input signal to a phase difference between a reference oscillator signal frequency and a clock signal frequency; and
a frequency section configured to communicate with the A/D converter and the D/A converter and operate at a frequency derived from the clock signal, wherein the frequency section provides the control input signal to the oscillator circuit. - View Dependent Claims (9, 10, 11)
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12. A receiver, comprising:
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an A/D converter;
an oscillator circuit configured to provide a sampling clock that is received by the A/D converter;
a digital data processing circuit configured to receive a digital data signal from the A/D converter; and
a frequency section coupled to the A/D converter, wherein the frequency section comprises a frequency converter stage that operates with a beat frequency derived from the sampling clock. - View Dependent Claims (13, 14)
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15. A transmitter, comprising:
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a D/A converter;
an oscillator circuit configured to provide a sampling clock that is received by the D/A converter;
a digital data processing circuit that provides a digital data signal to the D/A converter; and
a frequency section coupled to the D/A converter, wherein the frequency section comprises a frequency converter stage that operates with a beat frequency derived from the sampling clock. - View Dependent Claims (16, 17, 18, 19)
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20. A method of operating a receiver;
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correcting a clock signal by comparing a control input signal to a phase difference between a reference oscillator signal frequency that is derived from a crystal oscillator and a frequency of the clock signal;
converting a received signal into an analog signal using a beat frequency derived from the clock signal; and
converting the analog signal into a digital data signal using the frequency of the clock signal as a sampling frequency. - View Dependent Claims (21, 22)
- comprising;
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23. A method of operating a transmitter, comprising:
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correcting a clock signal by comparing a control input signal to a phase difference between a reference oscillator signal frequency that is derived from a crystal oscillator and a frequency of the clock signal;
converting a digital data signal into an analog signal using the frequency of the clock signal as a sampling frequency; and
converting the analog signal into a transmit signal using a beat frequency derived from the clock signal. - View Dependent Claims (24, 25)
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26. A method of operating a transceiver, comprising:
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correcting a clock signal by determining a phase difference between a reference oscillator signal frequency that is derived from a crystal oscillator and a frequency of the clock signal;
converting a received signal into a first analog signal using a beat frequency derived from the clock signal;
converting the first analog signal into a first digital data signal using the frequency of the clock signal as a sampling frequency;
converting a second digital data signal into a second analog signal using the frequency of the clock signal as the sampling frequency; and
converting the second analog signal into a transmit signal using the beat frequency that is derived from the clock signal. - View Dependent Claims (27, 28, 29)
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Specification