Semiconductor memory
First Claim
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1. A semiconductor memory comprising:
- a memory cell having first and second storage terminals storing information of logic levels complementary to each other;
a power supply wiring supplying a predetermined power supply voltage to said memory cell;
first and second pairs of bit lines each electrically connected to said first and second storage terminals of said memory cell, when selected; and
first and second word lines connected to said memory cell, said first pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said first word line, and said second pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said second word line, wherein said first and second pairs of bit lines and said power supply wiring are provided in parallel to each other, with said power supply wiring interposed between said first and second pairs of bit lines.
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Abstract
A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
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Citations
10 Claims
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1. A semiconductor memory comprising:
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a memory cell having first and second storage terminals storing information of logic levels complementary to each other;
a power supply wiring supplying a predetermined power supply voltage to said memory cell;
first and second pairs of bit lines each electrically connected to said first and second storage terminals of said memory cell, when selected; and
first and second word lines connected to said memory cell, said first pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said first word line, and said second pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said second word line, wherein said first and second pairs of bit lines and said power supply wiring are provided in parallel to each other, with said power supply wiring interposed between said first and second pairs of bit lines. - View Dependent Claims (2, 3)
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4. A semiconductor device comprising a two-port static memory cell including:
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a first inverter having an input connected to a first storage node and an output connected to a second storage node;
a second inverter having an input connected to said second storage node and an output connected to said first storage node;
a first transistor of first conductivity type having one end connected to said first storage node, the other end connected to a first bit line provided for a first port, and a gate electrode connected to a first word line;
a second transistor of said first conductivity type having one end connected to said first storage node, the other end connected to a second bit line provided for a second port and a gate electrode connected to a second word line;
a third transistor of said first conductivity type having one end connected to said second storage node, the other end connected to a third bit line provided for said first port and a gate electrode connected to said first word line; and
a fourth transistor of said first conductivity type having one end connected to said second storage node, the other end connected to a fourth bit line provided for said second port and a gate electrode connected to said second word line, wherein said first and second word lines are arranged in parallel to each other, said two-port static memory cell is divided into a first region of second conductivity type, a second region of said first conductivity type and a third region of said second conductivity type, arranged in this order in a direction of extension of said first and second word lines, said first to third regions respectively having transistors formed therein, said first transistor, said third transistor and a fifth transistor of said first conductivity type constituting said second inverter are arranged in said first region, a seventh transistor of said second conductivity type constituting said second inverter and an eighth transistor of said second conductivity type constituting said first inverter are arranged in said second region, and said second transistor, said fourth transistor and a sixth transistor of said first conductivity type constituting said first inverter are arranged in said third region. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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Specification