Dual-addressed rectifier storage device

• US RE41,733 E1
• Filed: 03/29/2001
• Issued: 09/21/2010
• Est. Priority Date: 03/05/1996
• Status: Expired due to Term

• Current Assignee: HGST, Inc. (Western Digital Corporation)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel R.
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US09/821,182
• Time in Patent Office: 3,463 Days
• Field of Search: 365/175, 365/105, 365/115, 365/239, 365/227, 345/82, 345/83
• US Class Current: 365/105
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/112 Read-only memory structures [ROM] and multistep manufacturing processes therefor

Abstract

A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable scalable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

Claims

1. A digital logic device comprising one or more electronic information storage means, and addressing means for accessing said storage means, wherein each said electronic information storage means comprises:

a plurality of generally parallel conductive means;

a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;

a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means with each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;

means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means to a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased;

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled; and

wherein said addressing means comprises;

means for controlling said means for electronically selecting conductive means of one said plurality of generally parallel conductive means and for electronically selecting conductive means of the other said plurality of generally parallel conductive means.

2. The digital logic device of claim 1, wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:

means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.

3. The digital logic device of claim 1, further comprising means for detecting a conducted current through said rectifying conductive means if present at said point of intersection.

4. The digital logic device circuit of claim 1 31, wherein one of said plurality of generally parallel conductive means the sets of conductive lines is a plurality of generally parallel doped regions within a semiconductor material.

6. The digital logic device circuit of claim 1 31, wherein said addressing means circuitry comprises means circuitry to sequentially select addressed storage locations.

7. The digital logic device circuit of claim 1 31, wherein said addressing means circuitry comprises means circuitry to randomly select addressed storage locations.

8. The digital logic device circuit of claim 1 31, further comprising display means for displaying alphanumeric or graphic information to its a user.

9. The digital logic device circuit of claim 1 31, further comprising input means to enable its user to alter its operation.

10. The digital logic device circuit of claim 1 31, wherein part or all of said one more electronic storage means are circuit is removable or replaceable.

11. The digital logic device circuit of claim 1 31, wherein output from the device circuit is in a digital format.

12. The digital logic device circuit of claim 1 31, wherein output from the device circuit is in an analog format.

13. The digital logic device circuit of claim 1 31, wherein output from the device circuit is in either a digital format or an analog format.

14. An electronic information storage device comprising:

a plurality of generally parallel conductive means;

a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;

a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;

means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.

15. The storage device of claim 14, wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:

means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.

16. The storage device of claim 14, further comprising means for detecting a conducted current through said rectifying conductive means if present at said point of intersection.

17. The storage device of claim 14, wherein one of said plurality of generally parallel conductive means is a plurality of generally parallel doped regions within a semiconductor material.

18. The storage device circuit of claim 17 5, wherein said rectifying conductive means between said plurality of generally parallel doped regions and a plurality of generally parallel metalized regions is nonlinear elements are of the metal-on-semiconductor junction type.

19. The storage device circuit of claim 17 5, wherein said rectifying conductive means between said plurality of generally parallel doped regions and a plurality of generally parallel metalized regions is nonlinear elements are of the p-n junction type.

20. The storage device of claim 14, wherein one of said plurality of generally parallel conductive means is a plurality of generally parallel metalized regions.

21. The storage device circuit of claim 14 31, wherein said rectifying conductive means is comprised by a transistor as the base-emitter junction nonlinear elements comprise base-emitter junctions of transistors.

22. The storage device circuit of claim 14 31, further comprising means for retaining the address of the information to be accessed.

23. The storage device circuit of claim 22, further comprising means for incrementing the retained address.

24. The storage device circuit of claim 22, further comprising means for setting the retained address.

25. An electronic information storage device comprising a plurality of storage means where each storage means comprises:

a plurality of generally parallel conductive means;

a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;

a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;

means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled;

where at least one of said plurality of generally parallel conductive means is common to more than one said storage means.

26. The storage device of claim 25, wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:

means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.

27. A semiconductor information storage device comprising:

a plurality of generally parallel conductive means;

a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means where one of said two pluralities of generally parallel conductive means is generally a surface layer of the semiconductor; and

a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection, and where any said presence or absence of a rectifying conductive means is determined by the leaving in place or the removal, respectively, of a portion of the surface layer conductive means.

28. An electronic array of selectable points comprising:

a plurality of conductive means;

a second plurality of conductive means;

a plurality of selectable points where a point of said plurality of selectable points is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of conductive means and each conductive means of the second said plurality of conductive means;

means for selecting a conductive means of one plurality of conductive means, and means for biasing the conductive means of the other plurality of conductive means such that each said selectable point present between a conductive means of said biased plurality of conductive means and a conductive means of the other said plurality of conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of conductive means by shifting the voltage of those biased conductive means that are to be disabled.

29. The electronic array of selectable points of claim 28, wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:

means for biasing the conductive means of the said one plurality of conductive means such that each said selectable point present between a conductive means of said biased plurality of conductive means and a conductive means of the other said plurality of conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of conductive means by shifting the voltage of those biased conductive means that are to be disabled.

30. The electronic array of selectable points of claim 28, wherein said each selectable point comprises a light emitting diode (LED) which will emit light when forward biased.

31. An information-storage circuit, the circuit comprising:

first and second sets of conductive lines overlapping with each other and defining storage locations at overlap regions;

a pattern of information-defining nonlinear elements, each nonlinear element connected to the first and second sets of conductive lines at an overlap region, presence or absence of a nonlinear element connection at a storage location defining a bit state at the location; and

address circuitry comprising a first pattern of rectifiers directly connected between the first set of conductive lines and a first set of address signal lines, application of an address to the first set of address signal lines causing the first pattern of rectifiers to disable all but one of the first set of conductive lines.

5. The digital logic device circuit of claim 4 31, wherein the other of said plurality of generally parallel conductive means one of the sets of conductive lines is a plurality of generally parallel metalized regions.

32. The circuit of claim 31 further comprising sensing circuitry for sensing the presence or absence of an information-defining nonlinear element connected to the selected one of the first set of conductive lines and at least a selected one of the second set of conductive lines to thereby determine the bit state at each storage location defined by selected conductive lines.

33. The circuit of claim 32 wherein the sensing circuitry is configured to sense current when said information-defining nonlinear element is not connected to the selected one of the first set of conductive lines and the selected one of the second set of conductive lines.

34. The circuit of claim 33 wherein the sensing circuitry comprises an output line connected to each of the first set of conductive lines by a sensing nonlinear element.

35. The circuit of claim 34 wherein the address circuitry comprises a first set of selectable disabling lines fewer in number than and connected to the first set of conductive lines by the first pattern of rectifiers, and circuitry for applying a second voltage to at least some of the first set of disabling lines to thereby disable all but one of the first set of conductive lines, the information-storage circuit further comprising additional address circuitry which itself comprises (i) a second set of selectable disabling lines fewer in number than and connected to the second set of conductive lines by a second pattern of rectifiers, and (ii) circuitry for applying a first voltage to at least some of the second set of disabling lines to thereby disable all but one of the second set of conductive lines, all of the rectifiers having a threshold activation voltage associated therewith, application of the threshold activation voltage across the rectifiers allowing current to flow therethrough.

36. The circuit of claim 35 further comprising a first series of voltage-drop elements connecting the first set of conductive lines to a circuitry for applying a first voltage and a second series of voltage drop elements connecting the second set of conductive lines to a circuitry for applying a second voltage.

37. The circuit of claim 36 wherein the first and second series of voltage drop elements are resistors.

38. The circuit of claim 36 wherein the first and second series of voltage drop elements are nonlinear elements.

39. The circuit of claim 38 wherein the nonlinear elements are rectifiers.

40. The circuit of claim 39, wherein the first and second sets of conductive lines are disposed on an integrated circuit chip, and the circuitry for applying the first voltage and the circuitry for applying the second voltage are disposed off of the integrated circuit chip and connected thereto.

41. The circuit of claim 36 wherein the second voltage is approximately a ground voltage.

42. The circuit of claim 32 further comprising a first series of voltage-drop elements connecting the first set of conductive lines to a circuitry for applying a first voltage and a second series of voltage drop elements connecting the second set of conductive lines to a circuitry for applying a second voltage.

43. The circuit of claim 42 wherein the first and second series of voltage drop elements are resistors.

44. The circuit of claim 42 wherein the first and second series of voltage drop elements are nonlinear elements.

45. The circuit of claim 44 wherein the nonlinear elements are rectifiers.

46. The circuit of claim 45, wherein the first and second sets of conductive lines are disposed on an integrated circuit chip, and the circuitry for applying the first voltage and the circuitry for applying the second voltage are disposed off of the integrated circuit chip and connected thereto.

47. The circuit of claim 42 wherein the second voltage is approximately a ground voltage.

48. The circuit of claim 31 wherein the all but one of the first set of conductive lines is disabled by shifting a voltage thereon.

49. The circuit of claim 31 further comprising additional address circuitry for disabling all but a selected one of the second set of conductive lines.

50. The circuit of claim 49 wherein the all but one of the second set of conductive lines is disabled by shifting a voltage thereon.

51. The circuit of claim 49 wherein:

the information-defining nonlinear elements have a threshold activation voltage associated therewith;

the address circuitry comprises circuitry for setting all but the selected one of the first set of conductive lines to a first voltage; and

the additional address circuitry comprises circuitry for setting all but the selected one of the second set of conductive lines to a second voltage, the first and second voltages differing by at least the threshold activation voltage.

52. The circuit of claim 51 wherein:

the address circuitry further comprises a first set of selectable disabling lines fewer in number than and connected to the first set of conductive lines by the first pattern of rectifiers, and circuitry for applying a third voltage to at least some of the first set of disabling lines to thereby disable all but one of the first set of conductive lines; and

the additional address circuitry further comprises a second set of selectable disabling lines fewer in number than and connected to the second set of conductive lines by a second pattern of rectifiers, and circuitry for applying a fourth voltage to at least some of the second set of disabling lines to thereby disable all but one of the second set of conductive lines.

53. The circuit of claim 52 wherein the third voltage is substantially equal to the second voltage and the fourth voltage is substantially equal to the first voltage.

54. The circuit of claim 53 wherein all of the rectifiers have said threshold activation voltage associated therewith, application of the threshold activation voltage across the rectifiers allowing current to flow therethrough.

55. The circuit of claim 54 wherein all of the nonlinear elements are rectifiers having an associated voltage drop corresponding to the threshold activation voltage, the first and second voltages differing by at least the rectifier voltage drop.

56. The circuit of claim 51 wherein the information-defining nonlinear elements are rectifiers having an associated voltage drop corresponding to the threshold activation voltage, the first and second voltages differing by at least the rectifier voltage drop so that an information-defining rectifier, if connected to the selected conductive lines, is forward biased.

57. The circuit of claim 51 wherein the second voltage is approximately a ground voltage.

58. The circuit of claim 31 further comprising a first series of voltage-drop elements connecting the first set of conductive lines to a circuitry for applying a first voltage and a second series of voltage drop elements connecting the second set of conductive lines to a circuitry for applying a second voltage.

59. The circuit of claim 58 wherein the first and second series of voltage drop elements are resistors.

60. The circuit of claim 58 wherein the first and second series of voltage drop elements are nonlinear elements.

61. The circuit of claim 60 wherein the nonlinear elements are rectifiers.

62. The circuit of claim 61, wherein the first and second sets of conductive lines are disposed on an integrated circuit chip, and the circuitry for applying the first voltage and the circuitry for applying the second voltage are disposed off of the integrated circuit chip and connected thereto.

63. The circuit of claim 58 wherein the second voltage is approximately a ground voltage.

64. The circuit of claim 31 wherein the circuit operates as a random access memory.

65. The circuit of claim 31 wherein the circuit operates as a read only memory.

66. The circuit of claim 31 wherein the circuit operates as a one-time-programmable read only memory.