Class B driver

• US RE41,831 E1
• Filed: 11/21/2005
• Issued: 10/19/2010
• Est. Priority Date: 05/23/2000
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Roo, Pierte
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US11/284,395
• Time in Patent Office: 1,793 Days
• Field of Search: 327/108, 327/126, 327/129, 327/132, 327/133, 327/134, 327/135, 327/136, 327/170, 341/143, 341/144, 341/153, 375/275, 375/276, 375/296, 375/297, 333/165, 333/166
• US Class Current: 341/144
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125
• CPC Class Codes: H03M 1/0881 by forcing a gradual change from one output level to the next, e.g. soft-start
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators

Abstract

A communication circuit, Ethernet controller card, and method comprises K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding analog control signal, wherein K is at least two; K voltage-to-current converters each providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and wherein the corresponding bi-level transmit signal components of each of the K voltage-to-current converters are combined to produce a J-level transmit signal, wherein J=K+1.

Claims

1. A communication circuit comprising:

a digital-to-analog converter to receive a digital control signal, and to provide an analog control signal, the digital-to-analog converter comprising

N current sources configured in a parallel arrangement,

wherein N is at least two, and

wherein each of the N current sources includes a respective control input,

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements,

wherein M is equal to N−

1,

wherein an output of the mth one of the M delay elements controls the control input of an m+1th one of the N current sources,

wherein an input of a first one of the M delay elements receives the digital control signal, and

wherein the analog control signal comprises the sum of the outputs of the N current sources; and

a voltage-to-current converter to provide a transmit signal based on the analog control signal.

2. The communication circuit of claim 1, wherein the M delay elements comprise at least one delay lock loop.

3. The communication circuit of claim 1, wherein the transmit signal is a Class B signal.

4. The communication circuit of claim 1, further comprising:

a low-pass filter to receive the analog control signal, and to provide a filtered analog control signal to the voltage-to-current converter.

5. The communication circuit of claim 4, wherein the low-pass filter comprises a single-pole filter.

6. The communication circuit of claim 1, wherein the voltage-to-current converter provides a replica of the transmit signal.

7. The communication circuit of claim 1, wherein the voltage-to-current converter comprises a voltage buffer.

8. The communication circuit of claim 1, wherein the communication circuit operates at up to gigabit speeds.

9. A communication circuit, comprising:

a digital-to-analog converter to receive a digital control signal, and to provide an analog control signal, the digital-to-analog converter comprising;

N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input,

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements, wherein M is equal to N−

1, wherein an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources, wherein an input of a first one of the M delay elements receives the digital control signal, and

wherein the analog control signal comprises the a sum of the outputs of the N current sources;

a voltage-to-current converter to provide a transmit signal based on the analog control signal,

wherein the voltage-to-current-converter provides a replica of the transmit signal;

a first sub-circuit having a composite input to receive a differential composite signal comprising the transmit signal, a replica input to receive a differential replica signal comprising the replica of the transmit signal, and a difference output to provide a differential difference signal representing a difference between the differential composite signal and the differential replica signal;

a second sub-circuit which produces first and second single-ended replica signals which together substantially comprise the differential replica signal; and

a third sub-circuit, which is coupled to the first and second sub-circuits, and which produces the differential replica signal from the first and second single-ended replica signals.

10. A communication circuit comprising:

K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding analog control signal, wherein K is at least two;

K voltage-to-current converters each providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and

wherein the corresponding bi-level transmit signal component of each of the K voltage-to-current converters are combined to produce a J-level transmit signal, wherein J=K+1.

11. The communication circuit of claim 10, wherein the J-level transmit signal is a Class B signal.

12. The communication circuit of claim 10, wherein each of the K digital-to-analog converters comprises:

N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input;

and

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements, wherein M is equal to N−

1, wherein an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources, wherein an input of a first one of the M delay elements receives the corresponding digital control signal.

13. The communication circuit of claim 12, wherein the M delay elements comprise at least one delay lock loop.

14. The communication circuit of claim 10, wherein the K voltage-to-current converters provide a replica of the J-level transmit signal.

15. The communication circuit of claim 10, wherein each of the K voltage-to-current converters comprises a voltage buffer.

16. The communication circuit of claim 10, wherein the communication circuit operates at up to gigabit speeds.

17. A communication circuit, comprising:

K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding analog control signal, wherein K is at least two;

K voltage-to-current converters each providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals;

wherein the corresponding bi-level transmit signal component of each of the K voltage-to-current converters are combined to produce a J-level transmit signal, wherein J=K+1,

wherein the K voltage-to-current converters provide a replica of the J-level transmit signal,

wherein the replica of the transmit signal comprises first and second single-ended replica signals;

a first sub-circuit which produces a differential replica signal from the first and second single-ended replica signals; and

a second sub-circuit coupled to the first sub-circuit and the voltage-to-current converters and having a composite input to receive a differential composite signal comprising the transmit signal, a replica input to receive the differential replica signal, and a difference output to provide a differential difference signal representing a difference between the differential composite signal and the differential replica signal.

18. A communication circuit comprising:

K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding transmit signal component, wherein K is at least two, and wherein each of the K digital-to-analog converters comprises

N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input,

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements, wherein M is equal to N−

1, wherein an output of the mth one of the M delay elements controls the control input of an m+1th one of the N current sources, wherein an input of a first one of the M delay elements receives the corresponding digital control signal, and

wherein the corresponding transmit signal component comprises the a sum of the outputs of the N current sources; and

wherein the corresponding transmit signal component of each of the K digital-to-analog converters are combined to produce a J-level transmit signal, wherein J=K +1.

19. The communication circuit of claim 18, wherein the M delay elements comprise at least one delay lock loop.

20. The communication circuit of claim 18, wherein the J-level transmit signal is a Class B signal.

21. The communication circuit of claim 18, wherein the communication circuit operates at up to gigabit speeds.

22. A communication circuit, comprising:

K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding transmit signal component, wherein K is at least two, and wherein each of the K digital-to-analog converters comprises;

N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input,

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements, wherein M is equal to N−

1, wherein an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources, wherein an input of a first one of the M delay elements receives the corresponding digital control signal, and

wherein the corresponding transmit signal component comprises the a sum of the outputs of the N current sources; and

wherein the corresponding transmit signal component of each of the K digital-to-analog converters are combined to produce a J-level transmit signal, wherein J=K+1; and

L digital-to-analog converters each receiving the corresponding digital control signal and each providing a corresponding replica transmit signal component,

wherein L=K; and

wherein the corresponding replica transmit signal component of each of the L digital-to-analog converters are combined to produce a J-level replica transmit signal.

23. An Ethernet controller comprising:

a digital-to-analog converter to receive a digital control signal, and to provide an analog control signal, the digital-to-analog converter comprising

N current sources configured in a parallel arrangement,

wherein N is at least two, and

wherein each of the N current sources includes a respective control input,

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements,

wherein M is equal to N−

1,

wherein an output of the mth one of the M delay elements controls the control input of an m+1th one of the N current sources,

wherein an input of a first one of the M delay elements receives the digital control signal, and

wherein the analog control signal comprises the sum of the outputs of the N current sources; and

a voltage-to-current converter to provide a transmit signal based on the analog control signal.

24. The Ethernet controller of claim 23, wherein the M delay elements comprise at least one delay lock loop.

25. The Ethernet controller of claim 23, wherein the transmit signal is a Class B signal.

26. The Ethernet controller of claim 23, further comprising:

a low-pass filter to receive the analog control signal, and to provide a filtered analog control signal to the voltage-to-current converter.

27. The Ethernet controller of claim 26, wherein the low-pass filter comprises a single-pole filter.

28. The Ethernet controller of claim 23, wherein the voltage-to-current converter provides a replica of the transmit signal.

29. The Ethernet controller of claim 23, wherein the voltage-to-current converter comprises a voltage buffer.

30. The Ethernet controller of claim 23, wherein the Ethernet controller operates at up to gigabit speeds.

31. An Ethernet controller, comprising:

a digital-to-analog converter to receive a digital control signal, and to provide an analog control signal, the digital-to-analog converter comprising;

N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input,

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements, wherein M is equal to N−

1, wherein an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources, wherein an input of a first one of the M delay elements receives the digital control signal, and

wherein the analog control signal comprises the a sum of the outputs of the N current sources;

a voltage-to-current converter to provide a transmit signal based on the analog control signal,

wherein the voltage-to-current converter provides a replica of the transmit signal;

a first sub-circuit having a composite input to receive a differential composite signal comprising the transmit signal, a replica input to receive a differential replica signal comprising the replica of the transmit signal, and a difference output to provide a differential difference signal representing a difference between the differential composite signal and the differential replica signal;

a second sub-circuit which produces first and second single-ended replica signals which together substantially comprise the differential replica signal; and

a third sub-circuit, which is coupled to the first and second sub-circuits, and which produces the differential replica signal from the first and second single-ended replica signals.

32. An Ethernet controller comprising:

K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding analog control signal, wherein K is at least two;

K voltage-to-current converters each providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and

wherein the corresponding bi-level transmit signal component of each of the K voltage-to-current converters are combined to produce a J-level transmit signal, wherein J=K+1.

33. The Ethernet controller of claim 32, wherein the J-level transmit signal is a Class B signal.

34. The Ethernet controller of claim 32, wherein each of the K digital-to-analog converters comprises:

N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input;

and

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements, wherein M is equal to N−

1, wherein an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources, wherein an input of a first one of the M delay elements receives the corresponding digital control signal.

35. The Ethernet controller of claim 34, wherein the M delay elements comprise at least one delay lock loop.

36. The Ethernet controller of claim 32, wherein the K voltage-to-current converters provide a replica of the J-level transmit signal.

37. The Ethernet controller of claim 32, wherein each of the K voltage-to-current converters comprises a voltage buffer.

38. The Ethernet controller of claim 32, wherein the Ethernet controller operates at up to gigabit speeds.

39. An Ethernet controller, comprising:

K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding analog control signal, wherein K is at least two;

K voltage-to-current converters each providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and

wherein the corresponding bi-level transmit signal component of each of the K voltage-to-current converters are combined to produce a J-level transmit signal, wherein J=K+1,

wherein the K voltage-to-current converters provide a replica of the J-level transmit signal,

wherein the replica of the transmit signal comprises first and second single-ended replica signals;

a first sub-circuit which produces a differential replica signal from the first and second single-ended replica signals; and

a second sub-circuit coupled to the first sub-circuit and the voltage-to-current converters and having a composite input to receive a differential composite signal comprising the transmit signal, a replica input to receive the differential replica signal, and a difference output to provide a differential difference signal representing a difference between the differential composite signal and the differential replica signal.

40. An Ethernet controller comprising:

K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding transmit signal component, wherein K is at least two, and wherein each of the K digital-to-analog converters comprises

N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input,

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements, wherein M is equal to N−

1, wherein an output of the mth one of the M delay elements controls the control input of an m+1th one of the N current sources, wherein an input of a first one of the M delay elements receives the corresponding digital control signal, and

wherein the corresponding transmit signal component comprises the a sum of the outputs of the N current sources; and

wherein the corresponding transmit signal component of each of the K digital-to-analog converters are combined to produce a J-level transmit signal, wherein J=K+1.

41. The Ethernet controller of claim 40, wherein the M delay elements comprise at least one delay lock loop.

42. The Ethernet controller of claim 40, wherein the J-level transmit signal is a Class B signal.

43. The Ethernet controller of claim 40, wherein the Ethernet controller operates at up to gigabit speeds.

44. An Ethernet controller, comprising:

K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding transmit signal component, wherein K is at least two, and wherein each of the K digital-to-analog converters comprises;

N current sources configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current sources includes a respective control input,

M delay elements, an mth one of the M delay elements including an input in communication with an m−

1th one of the M delay elements, wherein M is equal to N−

1, wherein an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources, wherein an input of a first one of the M delay elements receives the corresponding digital control signal, and

wherein the corresponding transmit signal component comprises the a sum of the outputs of the N current sources; and

wherein the corresponding transmit signal component of each of the K digital-to-analog converters are combined to produce a J-level transmit signal, wherein J=K+1; and

L digital-to-analog converters each receiving the corresponding digital control signal and each providing a corresponding replica transmit signal component,

wherein L=K; and

wherein the corresponding replica signal component of each of the L digital-to-analog converters are combined to produce a J-level replica transmit signal.

45. A communication circuit comprising:

digital-to-analog converter means for receiving a digital control signal, and for providing an analog control signal, the digital-to-analog converter means comprising

N current source means for providing current configured in a parallel arrangement,

wherein N is at least two, and

wherein each of the N current source means includes a respective means for inputting; and

M delay means for delaying, an mth one of the M delaying means including means for inputting in communication with an m−

1th one of the M delay means,

wherein M is equal to N−

1, and

wherein means for outputting of the mth one of the M delay means controls the inputting means of an m+1th one of the N current source means, and

wherein the analog control signal comprises the sum of the outputs of the N current source means; and

voltage-to-current converter means for providing a transmit signal based on the analog control signal.

46. The communication circuit of claim 45, wherein the M delay means comprise at least one delay lock loop.

47. The communication circuit of claim 45, wherein the transmit signal is a Class B signal.

48. The communication circuit of claim 45, further comprising:

filter means for receiving the analog control signal, and for providing a low-pass filtered analog control signal to the voltage-to-current converter means.

49. The communication circuit of claim 48, wherein the filter means comprises a single-pole filter.

50. The communication circuit of claim 45, wherein the voltage-to-current converter means provides a replica of the transmit signal.

51. The communication circuit of claim 45, wherein the voltage-to-current converter means comprises a voltage buffer.

52. The communication circuit of claim 45, wherein the communication circuit operates at up to gigabit speeds.

53. A communication circuit, comprising:

digital-to-analog converter means for receiving a digital control signal, and for providing an analog control signal, the digital-to-analog converter means comprising;

N current source means for providing current configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current source means includes a respective means for inputting; and

M delay means for delaying, an mth one of the M delaying delay means including means for inputting in communication with an m−

1th one of the M delay means, wherein M is equal to N−

1, and wherein means for outputting of the mth one of the M delay means is arranged in communication with the inputting means for inputting of an m+1th one of the N current source means, and

wherein the analog control signal comprises the a sum of the outputs of the N current source means;

voltage-to-current converter means for providing a transmit signal based on the analog control signal,

wherein the voltage-to-current converter means provides a replica of the transmit signal;

summing means for receiving a differential composite signal comprising the transmit signal, receiving a differential replica signal comprising the replica of the transmit signal, and providing a differential difference signal representing a difference between the differential composite signal and the differential replica signal;

replicating means for producing first and second single-ended replica signals which together substantially comprise the differential replica signal; and

converting means, which is coupled to the summing means and replicating means, for producing the differential replica signal from the first and second single-ended replica signals.

54. A communication circuit comprising:

K digital-to-analog converter means each for receiving a corresponding digital control signal and each for providing a corresponding analog control signal, wherein K is at least two;

K voltage-to-current converter means each for providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and

wherein the corresponding bi-level transmit signal components of each of the K voltage-to-current converter means are combined to produce a J-level transmit signal, wherein J=K+1.

55. The communication circuit of claim 54, wherein the J-level transmit signal is a Class B signal.

56. The communication circuit of claim 54, wherein each of the K digital-to-analog converter means comprises:

N current source means for providing current configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current source means includes a respective means for inputting; and

M delay means for delaying, an mth one of the M delaying delay means including means for inputting in communication with an m−

1th one of the M delay means, wherein M is equal to N−

1, and wherein means for outputting of the mth one of the M delay means is arranged in communication with the inputting means for inputting of an m+1th one of the N current source means.

57. The communication circuit of claim 56, wherein the M delay means comprise at least one delay lock loop.

58. The communication circuit of claim 54, wherein the K voltage-to-current converter means provide a replica of the J-level transmit signal.

59. The communication circuit of claim 54, wherein each of the K voltage-to-current converter means comprises a voltage buffer.

60. The communication circuit of claim 54, wherein the communication circuit operates at up to gigabit speeds.

61. A communication circuit, comprising:

K digital-to-analog converter means each for receiving a corresponding digital control signal and each for providing a corresponding analog control signal, wherein K is at least two;

K voltage-to-current converter means each for providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals,

wherein the corresponding bi-level transmit signal components of each of the K voltage-to-current converter means are combined to produce a J-level transmit signal, wherein J=K+1,

wherein the K voltage-to-current converter means provide a replica of the J-level transmit signal,

wherein the replica of the transmit signal comprises first and second single-ended replica signals;

converter means for producing a differential replica signal from the first and second single-ended replica signals; and

summing means, coupled to the converter means and the voltage-to-current converter means, for receiving a differential composite signal comprising the transmit signal, receiving the differential replica signal, and providing a differential difference signal representing a difference between the differential composite signal and the differential replica signal.

62. A communication circuit comprising:

K digital-to-analog converter means each for receiving a corresponding digital control signal and each for providing a corresponding transmit signal component, wherein K is at least two, and wherein at least one each of the K digital-to-analog converter means comprises

N current source means for providing current configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current source means includes a respective means for inputting; and

M delay means for delaying, an mth one of the M delaying delay means including means for inputting in communication with an m−

1th one of the M delay means, wherein M is equal to N−

1, and wherein means for outputting of the mth one of the M delay means controls the inputting means for inputting of an m+1th one of the N current source means, and

wherein the corresponding transmit signal component comprises the a sum of the outputs of the N current sources; and

wherein the corresponding transmit signal components of each of the K digital-to-analog converter means are combined to produce a J-level transmit signal, wherein J=K+1.

63. The communication circuit of claim 62, wherein the M delay means comprise at least one delay lock loop.

64. The communication circuit of claim 62, wherein the J-level transmit signal is a Class B signal.

65. The communication circuit of claim 62, wherein the communication circuit operates at up to gigabit speeds.

66. A communication circuit, comprising:

K digital-to-analog converter means each for receiving a corresponding digital control signal and each for providing a corresponding transmit signal component,

wherein K is at least two, and

wherein at least one each of the K digital-to-analog converter means comprises;

N current source means for providing current configured in a parallel arrangement,

wherein N is at least two, and

wherein each of the N current source means includes a respective means for inputting, and

M delay means for delaying, an mth one of the M delaying delay means including means for inputting in communication with an m−

1th one of the M delay means,

wherein M is equal to N−

1, and

wherein means for outputting of the mth one of the M delay means is arranged in communication with the inputting means for inputting of an m+1th one of the N current source means,

wherein the corresponding transmit signal component comprises the a sum of the outputs of the N current sources, and

wherein the corresponding transmit signal components of each of the K digital-to-analog converter means are combined to produce a J-level transmit signal wherein J=K+1; and

L digital-to-analog converter means each for receiving the corresponding digital control signal and each for providing a corresponding replica transmit signal component,

wherein L=K, and

wherein the corresponding replica transmit signal components of each of the L digital-to-analog converters are combined to produce a J-level replica transmit signal.

67. An Ethernet controller comprising:

digital-to-analog converter means for receiving a digital control signal, and for providing an analog control signal, the digital-to-analog converter means comprising

N current source means for providing current configured in a parallel arrangement,

wherein N is at least two, and

wherein each of the N current source means includes a respective means for inputting; and

M delay means for delaying, an mth one of the M delaying means including means for inputting in communication with an m−

1th one of the M delay means,

wherein M is equal to N−

1, and

wherein means for outputting of the mth one of the M delay means controls the inputting means of an m+1th one of the N current source means, and

wherein the analog control signal comprises the sum of the outputs of the N current source means; and

voltage-to-current converter means for providing a transmit signal based on the analog control signal.

68. The Ethernet controller of claim 67, wherein the M delay means comprise at least one delay lock loop.

69. The Ethernet controller of claim 67, wherein the transmit signal is a Class B signal.

70. The Ethernet controller of claim 67, further comprising:

filter means for receiving the analog control signal, and for providing a low-pass filtered analog control signal to the voltage-to-current converter means.

71. The Ethernet controller of claim 70, wherein the filter means comprises a single-pole filter.

72. The Ethernet controller of claim 67, wherein the voltage-to-current converter means provides a replica of the transmit signal.

73. The Ethernet controller of claim 67, wherein the voltage-to-current converter means comprises a voltage buffer.

74. The Ethernet controller of claim 67, wherein the Ethernet controller operates at up to gigabit speeds.

75. An Ethernet controller, comprising:

digital-to-analog converter means for receiving a digital control signal, and for providing an analog control signal, the digital-to-analog converter means comprising;

N current source means for providing current configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current source means includes a respective means for inputting; and

M delay means for delaying, an mth one of the M delaying delay means including means for inputting in communication with an m−

1th one of the M delay means, wherein M is equal to N−

1, and wherein means for outputting of the mth one of the M delay means is arranged in communication with the inputting means for inputting of an m+1th one of the N current source means, and

wherein the analog control signal comprises the a sum of the outputs of the N current source means;

voltage-to-current converter means for providing a transmit signal based on the analog control signal,

wherein the voltage-to-current converter means provides a replica of the transmit signal;

summing means for receiving a differential composite signal comprising the transmit signal, receiving a differential replica signal comprising the replica of the transmit signal, and providing a differential difference signal representing a difference between the differential composite signal and the differential replica signal;

replicating means for producing first and second single-ended replica signals which together substantially comprise the differential replica signal; and

converting means, which is coupled to the summing means and replicating means, for producing the differential replica signal from the first and second single-ended replica signals.

76. An Ethernet controller comprising:

K digital-to-analog converter means each for receiving a corresponding digital control signal and each for providing a corresponding analog control signal, wherein K is at least two;

K voltage-to-current converter means each for providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and

wherein the corresponding bi-level transmit signal components of each of the K voltage-to-current converter means are combined to produce a J-level transmit signal, wherein J=K+1.

77. The Ethernet controller of claim 76, wherein the J-level transmit signal is a Class B signal.

78. The Ethernet controller of claim 76, wherein each of the K digital-to-analog converter means comprises:

N current source means for providing current configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current source means includes a respective means for inputting; and

M delay means for delaying, an mth one of the M delaying delay means including means for inputting in communication with an m−

1th one of the M delay means, wherein M is equal to N−

1, and wherein means for outputting of the mth one of the M delay means is arranged in communication with the inputting means for inputting of an m+1th one of the N current source means.

79. The Ethernet controller of claim 78, wherein the M delay means comprise at least one delay lock loop.

80. The Ethernet controller of claim 76, wherein the K voltage-to-current converter means provide a replica of the J-level transmit signal.

81. The Ethernet controller of claim 76, wherein each of the K voltage-to-current converter means comprises a voltage buffer.

82. The Ethernet controller of claim 76, wherein the Ethernet controller operates at up to gigabit speeds.

83. An Ethernet controller, comprising:

K digital-to-analog converter means each for receiving a corresponding digital control signal and each for providing a corresponding analog control signal, wherein K is at least two;

K voltage-to-current converter means each for providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals,

wherein the corresponding bi-level transmit signal components of each of the K voltage-to-current converter means are combined to produce a J-level transmit signal, wherein J=K+1,

wherein the K voltage-to-current converter means provide a replica of the J-level transmit signal,

wherein the replica of the transmit signal comprises first and second single-ended replica signals;

converter means for producing a differential replica signal from the first and second single-ended replica signals; and

summing means, coupled to the converter means and the voltage-to-current converter means, for receiving a differential composite signal comprising the transmit signal, receiving the differential replica signal, and providing a differential difference signal representing a difference between the differential composite signal and the differential replica signal.

84. An Ethernet controller comprising:

K digital-to-analog converter means each for receiving a corresponding digital control signal and each for providing a corresponding transmit signal component, wherein K is at least two, and wherein at least one each of the K digital-to-analog converter means comprises

N current source means for providing current configured in a parallel arrangement, wherein N is at least two, and wherein each of the N current source means includes a respective means for inputting, and

M delay means for delaying, an mth one of the M delaying delay means including means for inputting in communication with an m−

1th one of the M delay means, wherein M is equal to N−

1, and wherein means for outputting of the mth one of the M delay means controls the inputting means for inputting of an m+1th one of the N current source means,

wherein the corresponding transmit signal component comprises the a sum of the outputs of the N current sources; and

wherein the corresponding transmit signal components of each of the K digital-to-analog converter means are combined to produce a J-level transmit signal, wherein J=K+1.

85. The Ethernet controller of claim 84, wherein the M delay means comprise at least one delay lock loop.

86. The Ethernet controller of claim 84, wherein the J-level transmit signal is a Class B signal.

87. The Ethernet controller of claim 84, wherein the Ethernet controller operates at up to gigabit speeds.

88. An Ethernet controller, comprising:

K digital-to-analog converter means each for receiving a corresponding digital control signal and each for providing a corresponding transmit signal component,

wherein K is at least two, and

wherein at least one each of the K digital-to-analog converter means comprises;

N current source means for providing current configured in a parallel arrangement,

wherein N is at least two, and

wherein each of the N current source means includes a respective means for inputting, and

M delay means for delaying, an mth one of the M delaying delay means including means for inputting in communication with an m−

1th one of the M delay means,

wherein M is equal to N−

1, and

wherein means for outputting of the mth one of the M delay means is arranged in communication with the inputting means for inputting of an m+1th one of the N current source means,

wherein the corresponding transmit signal component comprises the a sum of the outputs of the N current sources, and

wherein the corresponding transmit signal components of each of the K digital-to-analog converter means are combined to produce a J-level transmit signal, wherein J=K+1; and

L digital-to-analog converter means each for receiving the corresponding digital control signal and each for providing a corresponding replica transmit signal component, wherein L=K, and

wherein the corresponding replica transmit signal components of each of the L digital-to-analog converters are combined to produce a J-level replica transmit signal.

89. A communication method comprising:

receiving a digital control signal;

providing an analog control signal in accordance with the digital control signal, comprising

supplying N sources of current, wherein N is at least two;

controlling the supply of current from each of the N sources of current;

delaying current from M of the N sources of current,

where M is equal to N−

1, and

wherein an output of an mth one of M delaying steps controls an m+1th one of the N sources of current; and

summing the delayed currents,

wherein the analog control signal comprises the sum of the delayed currents; and

providing a transmit signal based on the analog control signal.

90. The communication method of claim 89, wherein the transmit signal is a Class B signal.

91. The communication method of claim 89, further comprising:

low-pass filtering the analog control signal; and

wherein the transmit signal is based on the low-pass filtered analog control signal.

92. The communication method of claim 91, wherein low-pass filtering the analog control signal comprises single-pole filtering the analog control signal.

93. The communication method of claim 89, further comprising providing a replica of the transmit signal.

94. The communication method of claim 89, wherein the communication method operates at up to gigabit speeds.

95. A communication method, comprising the steps of:

receiving a digital control signal;

providing an analog control signal in accordance with the digital control signal, comprising the steps of;

supplying N sources of current, wherein N is at least two;

controlling the supply of current from each of the N sources of current;

delaying current from M of the N sources of current, where M is equal to N−

1; and

summing the delayed currents,

wherein the analog control signal comprises the a sum of the delayed currents;

providing a transmit signal based on the analog control signal;

providing a replica of the transmit signal;

receiving a differential composite signal comprising the transmit signal;

receiving a differential replica signal comprising the replica of the transmit signal;

providing a differential difference signal representing a difference between the differential composite signal and the differential replica signal;

producing first and second single-ended replica signals which together substantially comprise the differential replica signal; and

producing the differential replica signal from the first and second single-ended replica signals.

96. A communication method comprising:

receiving K digital control signals, wherein K is at least two;

providing a corresponding analog control signal for each of the K digital control signals;

providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and

combining the corresponding bi-level transmit signal components to produce a J-level transmit signal, wherein J=K+1.

97. The communication method of claim 96, wherein the J-level transmit signal is a Class B signal.

98. The communication method of claim 96, wherein providing a corresponding analog control signal comprises:

supplying N sources of current, wherein N is at least two;

controlling the supply of current from each of the N sources of current;

delaying current from M of the N sources of current, where M is equal to N−

1; and

summing the delayed currents.

99. The communication method of claim 96, further comprising:

providing a replica of the J-level transmit signal.

100. The communication method of claim 96, wherein the communication method operates at up to gigabit speeds.

101. A communication method, comprising the steps of:

receiving K digital control signals, wherein K is at least two;

providing a corresponding analog control signal for each of the K digital control signals;

providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals;

combining the corresponding bi-level transmit signal components to produce a i-level transmit signal, wherein J=K+1;

providing a replica of the J-level transmit signal,

wherein the replica of the transmit signal comprises first and second single-ended replica signals;

producing a differential replica signal from the first and second single-ended replica signals; and

providing a differential difference signal representing a difference between the differential replica signal and a differential composite signal comprising the transmit signal.

102. A communication method comprising:

receiving K digital control signals, wherein K is at least two;

providing a corresponding transmit signal component for each of the K digital control signals, comprising

supplying N sources of current, wherein N is at least two,

controlling the supply of current from each of the N sources of current,

delaying current from M of the N sources of current,

where M is equal to N−

1, and

wherein an output of an mth one of M delaying steps controls an m+1th one of the N sources of current, and

summing the delayed currents,

wherein the corresponding transmit signal component comprises the a sum of the delayed currents; and

combining the corresponding transmit signal components to produce a J-level transmit signal, wherein J=K+1.

103. The communication method of claim 102, wherein the J-level transmit signal is a Class B signal.

104. The communication method of claim 102, wherein the communication method operates at up to gigabit speeds.

105. A communication method, comprising the steps of:

receiving K digital control signals, wherein K is at least two;

providing a corresponding transmit signal component for each of the K digital control signals, comprising the steps of;

supplying N sources of current, wherein N is at least two;

controlling the supply of current from each of the N sources of current;

delaying current from M of the N sources of current, where M is equal to N−

1; and

summing the delayed currents,

wherein the corresponding transmit signal component comprises the a sum of the delayed currents;

combining the corresponding transmit signal components to produce a J-level transmit signal, wherein J=K+1;

receiving the corresponding digital control signals;

providing a corresponding replica transmit signal component for each of the corresponding digital control signals; and

combining the corresponding replica transmit signal components to produce a J-level replica transmit signal.

106. A communication circuit, comprising:

a plurality of sets of digital-to-analog converters (DACs),

wherein the plurality of sets of DACs are arranged in parallel,

wherein each DAC within a set of DACs is configured to receive a digital signal and to provide an output signal, and

wherein each DAC comprises;

N current sources arranged in parallel,

wherein N is at least two,

wherein each of the N current sources includes a respective control input, and

wherein the output signal provided by each DAC comprises a sum of outputs of the N current sources; and

M delay elements,

wherein an mth one of the M delay elements includes an input in communication with an m−

1th one of the M delay elements,

wherein M is equal to N−

1,

wherein an output of the mth one of the M delay elements controls the control input of an m+1th one of the N current sources,

wherein an input of a first one of the M delay elements receives the digital signal, and

wherein a sum of each output signal from a respective one of the plurality of sets of DACs forms a transmit signal, and

wherein a first set of the plurality of sets of DACs is configured to produce a first polarity of a differential replica signal comprising replicas of transmit signal components output by the DACs of the first set.

107. The communication circuit of claim 106, comprising:

a summer for summing each output signal from the respective one of the plurality of sets of DACs.

108. The communication circuit of claim 106, wherein the plurality of sets of DACs comprises K sets of DACs, and

wherein the transmit signal comprises a J-level transmit signal,

wherein J=K+1.

109. The communication circuit of claim 106, wherein each of the N current sources of each DAC is arranged in a differential configuration.

110. The communication circuit of claim 106, wherein the M delay elements of each DAC comprise at least one delay lock loop.

111. The communication circuit of claim 106, wherein the transmit signal comprises a Class B signal.

112. The communication circuit of claim 106, wherein a said first set of the plurality of sets of DACs is configured to produce a first polarity of a differential composite signal comprising transmit signal components output by the DACs of the first set, and configured to produce a first polarity of a differential replica signal comprising replicas of the transmit signal components output by the DACs of the first set .

113. The communication circuit of claim 112, wherein a second set of the plurality of sets of DACs is configured to produce a second polarity of the differential composite signal comprising transmit signal components output by the DACs of the second set, and configured to produce a second polarity of the differential replica signal comprising replicas of the transmit signal components output by the DACs of the second set.

114. The communication circuit of claim 113, wherein a differential difference signal is produced comprising a difference between the differential composite signal and the differential replica signal.

115. The communication circuit of claim 114, wherein the differential difference signal comprises a receive signal.

116. The communication circuit of claim 106, wherein the communication circuit operates at up to gigabit speeds.

117. A communication circuit, comprising:

a plurality of sets of digital-to-analog converter (DAC) means,

wherein the plurality of sets of DAC means are arranged in parallel,

wherein each DAC means within a set of DAC means is configured to receive a digital signal and to provide an output signal, and

wherein each DAC means comprises;

N current source means arranged in parallel,

wherein N is at least two,

wherein each of the N current source means includes a respective means for inputting, and

wherein the output signal provided by each DAC means comprises a sum of outputs of the N current source means; and

M delay means,

wherein an mth one of the M delay means includes a means for inputting in communication with an m−

1th one of the M delay means,

wherein M is equal to N−

1,

wherein means for outputting of the mth one of the M delay means controls the inputting means for inputting of an m+1th one of the N current source means,

wherein the inputting means for inputting of a first one of the M delay elements means receives the digital signal, and

wherein a sum of each output signal from a respective one of the plurality of sets of DAC means forms a transmit signal, and

wherein a first set of the plurality of sets of DAC means is configured to produce a first polarity of a differential replica signal comprising replicas of the transmit signal components output by the DAC means of the first set.

118. The communication circuit of claim 117, comprising:

means for summing each output signal from the respective one of the plurality of sets of DAC means.

119. The communication circuit of claim 117, wherein the plurality of sets of DAC means comprises K sets of DAC means, and

wherein the transmit signal comprises a J-level transmit signal,

wherein J=K+1.

120. The communication circuit of claim 117, wherein each of the N current source means of each DAC means is arranged in a differential configuration.

121. The communication circuit of claim 117, wherein the M delay means of each DAC means comprise at least one delay lock loop means.

122. The communication circuit of claim 117, wherein the transmit signal comprises a Class B signal.

123. The communication circuit of claim 117, wherein a said first set of the plurality of sets of DAC means is configured to produce a first polarity of a differential composite signal comprising transmit signal components output by the DAC means of the first set, and configured to produce a first polarity of a differential replica signal comprising replicas of the transmit signal components output by the DAC means of the first set .

124. The communication circuit of claim 123, wherein a second set of the plurality of sets of DAC means is configured to produce a second polarity of the differential composite signal comprising transmit signal components output by the DAC means of the second set, and configured to produce a second polarity of the differential replica signal comprising replicas of the transmit signal components output by the DAC means of the second set.

125. The communication circuit of claim 124, wherein a differential difference signal is produced comprising a difference between the differential composite signal and the differential replica signal.

126. The communication circuit of claim 125, wherein the differential difference signal comprises a receive signal.

127. The communication circuit of claim 117, wherein the communication circuit operates at up to gigabit speeds.

128. An Ethernet controller, comprising:

a plurality of sets of transceivers,

wherein the plurality of sets of transceivers are arranged in parallel,

wherein each transceiver within a set of transceivers is configured to receive a digital signal and to provide an output signal, and

wherein each transceiver comprises;

N current sources arranged in parallel,

wherein N is at least two,

wherein each of the N current sources includes a respective control input, and

wherein the output signal provided by each transceiver comprises a sum of outputs of the N current sources; and

M delay elements,

wherein an mth one of the M delay elements includes an input in communication with an m−

1th one of the M delay elements,

wherein M is equal to N−

1,

wherein an output of the mth one of the M delay elements controls the control input of an m+1th one of the N current sources,

wherein an input of a first one of the M delay elements receives the digital signal, and

wherein a sum of each output signal from a respective one of the plurality of sets of transceivers forms a transmit signal, and

wherein a first set of the plurality of sets of transceivers is configured to produce a first polarity of a differential replica signal comprising replicas of the transmit signal components output by the transceivers of the first set.

129. The Ethernet controller of claim 128, comprising:

a summer for summing each output signal from the respective one of the plurality of sets of transceivers.

130. The Ethernet controller of claim 128, wherein the plurality of sets of transceivers comprises K sets of transceivers, and

wherein the transmit signal comprises a J-level transmit signal,

wherein J=K+1.

131. The Ethernet controller of claim 128, wherein each of the N current sources of each transceiver is arranged in a differential configuration.

132. The Ethernet controller of claim 128, wherein the M delay elements of each transceiver comprise at least one delay lock loop.

133. The Ethernet controller of claim 128, wherein the transmit signal comprises a Class B signal.

134. The Ethernet controller of claim 128, wherein a said first set of the plurality of sets of transceivers is configured to produce a first polarity of a differential composite signal comprising transmit signal components output by the transceivers of the first set, and configured to produce a first polarity of a differential replica signal comprising replicas of the transmit signal components output by the transceivers of the first set .

135. The Ethernet controller of claim 134, wherein a second set of the plurality of sets of transceivers is configured to produce a second polarity of the differential composite signal comprising transmit signal components output by the transceivers of the second set, and configured to produce a second polarity of the differential replica signal comprising replicas of the transmit signal components output by the transceivers of the second set.

136. The Ethernet controller of claim 135, wherein a differential difference signal is produced comprising a difference between the differential composite signal and the differential replica signal.

137. The Ethernet controller of claim 136, wherein the differential difference signal comprises a receive signal.

138. The Ethernet controller of claim 128, wherein the Ethernet controller operates at up to gigabit speeds.

139. An Ethernet controller, comprising:

a plurality of sets of transceiver means,

wherein the plurality of sets of transceiver means are arranged in parallel,

wherein each transceiver means within a set of transceiver means is configured to receive a digital signal and to provide an output signal, and

wherein each transceiver means comprises;

N current source means arranged in parallel,

wherein N is at least two,

wherein each of the N current source means includes a respective means for inputting, and

wherein the output signal provided by each transceiver means comprises a sum of outputs of the N current source means; and

M delay means,

wherein an mth one of the M delay means includes a means for inputting in communication with an m−

1th one of the M delay means,

wherein M is equal to N−

1,

wherein means for outputting of the mth one of the M delay means controls the inputting means for inputting of an m+1th one of the N current source means,

wherein the inputting means for inputting of a first one of the M delay elements means receives the digital signal, and

wherein a sum of each output signal from a respective one of the plurality of sets of transceiver means forms a transmit signal, and

wherein a first set of the plurality of sets of transceiver means is configured to produce a first polarity of a differential replica signal comprising replicas of transmit signal components output by the transceiver means of the first set.

140. The Ethernet controller of claim 139, comprising:

means for summing each output signal from the respective one of the plurality of sets of transceiver means.

141. The Ethernet controller of claim 139, wherein the plurality of sets of transceiver means comprises K sets of transceiver means, and

wherein the transmit signal comprises a J-level transmit signal,

wherein J=K+1.

142. The Ethernet controller of claim 139, wherein each of the N current source means of each transceiver means is arranged in a differential configuration.

143. The Ethernet controller of claim 139, wherein the M delay means of each transceiver means comprise at least one delay lock loop means.

144. The Ethernet controller of claim 139, wherein the transmit signal comprises a Class B signal.

145. The Ethernet controller of claim 139, wherein a said first set of the plurality of sets of transceiver means is configured to produce a first polarity of a differential composite signal comprising transmit signal components output by the transceiver means of the first set, and configured to produce a first polarity of a differential replica signal comprising replicas of the transmit signal components output by the transceiver means of the first set .

146. The Ethernet controller of claim 145, wherein a second set of the plurality of sets of transceiver means is configured to produce a second polarity of the differential composite signal comprising transmit signal components output by the transceiver means of the second set, and configured to produce a second polarity of the differential replica signal comprising replicas of the transmit signal components output by the transceiver means of the second set.

147. The Ethernet controller of claim 146, wherein a differential difference signal is produced comprising a difference between the differential composite signal and the differential replica signal.

148. The Ethernet controller of claim 147, wherein the differential difference signal comprises a receive signal.

149. The Ethernet controller of claim 139, wherein the Ethernet controller operates at up to gigabit speeds.

150. A communication method, comprising the steps of:

a.) receiving K digital signals, wherein K is at least two;

b.) providing K corresponding transmit signal components in accordance with each of the K digital signals,

wherein for each transmit signal component, step (b) comprises the steps of;

b1.) supplying N sources of current,

wherein N is at least two;

b2.) controlling the supply of current from each of the N sources of current;

b3.) delaying current from M of the N sources of current,

wherein M is equal to N−

1, and

wherein an output of an mth one of M delaying steps controls an m+1th one of the N sources of current; and

b4.) summing the delayed currents; and

c.) combining the K corresponding transmit signal components to produce a J-level transmit signal.

151. The method of claim 150, wherein J=K+1.

152. The method of claim 150, wherein the transmit signal comprises a Class B signal.

153. The method of claim 150, comprising the steps of:

receiving a first polarity of a differential composite signal comprising transmit signal components output by a first set of the a plurality of parallel transceiver sets; and

receiving a first polarity of a differential replica signal comprising replicas of the transmit signal components output by the first set of the plurality of parallel transceiver sets.

154. The method of claim 153, comprising the steps of:

receiving a second polarity of the differential composite signal comprising transmit signal components output by a second set of the plurality of parallel transceiver sets; and

receiving a second polarity of the differential replica signal comprising replicas of the transmit signal components output by the second set of the plurality of parallel transceiver sets.

155. The method of claim 154, comprising the step of:

producing a differential difference signal comprising a difference between the differential composite signal and the differential replica signal.

156. The method of claim 155, wherein the differential difference signal comprises a receive signal.