Systems and methods for self-test of a radar altimeter
First Claim
1. A radar altimeter system including a transmitter having a Direct Digital Synthesizer (DDS) and a Digital Phase Lock Loop, the system comprising:
- a first component configured to generate a voltage signal derived by comparing a fixed reference frequency to a ramped frequency signal generated by the DDS based on a clock-based reference signal;
a second component configured to integrate the generated voltage signal over a predefined range of clock signals;
a third component configured to sample the integration at a previously defined clock tick;
a fourth component configured to compare the sample to a desired value; and
a fifth component configured to provide an indication that the radar altimeter is malfunctioning if the comparison exceeds a predefined threshold value.
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Abstract
Systems and methods for testing a signal generated by a Direct Digital Synthesizer (DDS) in a radar altimeter. In an embodiment of the method, a voltage signal derived by comparing a fixed reference frequency to a ramped frequency signal generated by the DDS based on a clock-based reference signal is generated. The generated voltage signal is integrated over a predefined range of clock signals. The integration is sampled at a previously defined clock tick. The sample is compared to a desired value and an indication that the radar altimeter is malfunctioning is provided if the comparison exceeds a predefined threshold value. The radar altimeter system is deactivated if an indication that the radar altimeter is malfunctioning has been provided.
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Citations
17 Claims
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1. A radar altimeter system including a transmitter having a Direct Digital Synthesizer (DDS) and a Digital Phase Lock Loop, the system comprising:
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a first component configured to generate a voltage signal derived by comparing a fixed reference frequency to a ramped frequency signal generated by the DDS based on a clock-based reference signal;
a second component configured to integrate the generated voltage signal over a predefined range of clock signals;
a third component configured to sample the integration at a previously defined clock tick;
a fourth component configured to compare the sample to a desired value; and
a fifth component configured to provide an indication that the radar altimeter is malfunctioning if the comparison exceeds a predefined threshold value. - View Dependent Claims (2, 3)
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4. A method for testing a signal generated by a Direct Digital Synthesizer (DDS) in a radar altimeter, the method comprising:
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generating a voltage signal derived by comparing a fixed reference frequency to a ramped frequency signal generated by the DDS based on a clock-based reference signal;
integrating the generated voltage signal over a predefined range of clock signals;
sampling the integration at a previously defined clock tick;
comparing the sample to a desired value; and
providing an indication that the radar altimeter is malfunctioning if the comparison exceeds a predefined threshold value. - View Dependent Claims (5, 6)
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7. A method for testing a signal generated by a Direct Digital Synthesizer (DDS) in a radar altimeter, the method comprising:
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activating the radar altimeter in a normal mode of operation;
integrating a generated voltage signal between a turnaround point and a clock tick;
comparing a detected integration value to a reference voltage value; and
deactivating the radar altimeter system if the comparison is outside a predefined threshold value. - View Dependent Claims (8, 9, 10, 11)
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12. A radar altimeter system including a transmitter having a Direct Digital Synthesizer, (DDS) and a Digital Phase Lock Loop, the system comprising:
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a first component configured to generate a voltage signal derived by comparing a fixed reference frequency signal to a ramped frequency signal generated by the DDS based on a clock-based reference signal;
a second component configured to integrate the generated voltage signal over a predefined range of clock ticks;
a third component configured to generate an output signal representing a comparison of the integration to a desired value;
a fourth component configured to sample the comparison at a previously defined clock tick; and
a fifth component configured to provide an indication that the radar altimeter is malfunctioning if the comparison exceeds a predefined threshold value. - View Dependent Claims (13, 14)
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15. A method for testing a signal generated by a Direct Digital Synthesizer, (DDS) in a radar altimeter, the method comprising:
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generating a voltage signal derived by comparing a fixed reference frequency signal to a ramped frequency signal generated by the DDS based on a clock-based reference signal;
integrating the generated voltage signal over a predefined range of clock signals;
generating an output signal representing a comparison of the integration at a previously defined clock tick to a desired value; and
providing an indication that the radar altimeter is malfunctioning if the comparison exceeds a predefined threshold value. - View Dependent Claims (16, 17)
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Specification