Compact active pixel with low-noise image formation

• US RE43,314 E1
• Filed: 05/03/2007
• Issued: 04/17/2012
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: AltaSens, Inc. (JVC Kenwood Corporation)
• Inventors: Kozlowski, Lester J.
• Primary Examiner(s): Ye, Lin
• Assistant Examiner(s): HSU, AMY R
• Application Number:
  US11/800,070
• Time in Patent Office: 1,811 Days
• Field of Search: 348/308, 348/301, 348/294
• US Class Current: 348/308
• CPC Class Codes: H04N 5/363 applied to reset noise, e.g. KTC noise related to CMOS structures

Abstract

A low-noise active pixel circuit is disclosed that efficiently suppresses reset (kTC) noise by using a compact preamplifier consisting of a photodetector and only three transistors of identical polarity, in conjunction with ancillary circuits located on an imager'"'"'s periphery. The use of only three transistors with a tapered reset signal allows the optical area to be increased, while still providing a low-noise imager.

Claims

1. An active pixel sensor circuit comprising:

a photodetector;

an access transistor connected to the photodetector;

an electronically reconfigurable transistor, successively operated as a source follower driver and a feedback amplifier, connected to an output of the access transistor and to a signal output bus;

a reset transistor connected between the access transistor and the electronically reconfigurable transistor, wherein the reset transistor is reset with a tapered reset signal; and

a first column buffer connected to the electronically reconfigurable transistor and to the reset transistor, the first column buffer comprising;

a first switch transistor connected to the reset transistor;

and a second switch transistor connected to the electronically reconfigurable transistor;

wherein during a reset operation, the first and second switch transistors connect transistor connects the reset transistor with the electronically reconfigurable transistor to form a feedback path.

2. The circuit of claim 1, wherein the transistors are MOSFETs of identical polarity.

3. The circuit of claim 2, further comprising a second column buffer connected to the signal output bus.

4. The circuit of claim 3, further comprising a row disable transistor connected to the reset transistor.

5. The circuit of claim 4, wherein the first column buffer, second column buffer and row disable transistor are connected to a plurality of active pixel sensor circuits.

6. The circuit of claim 5, wherein the electronically reconfigurable transistor operates as a driver of a source follower amplifier when a signal from the photodetector is being read out on a row-by-row basis, and operates as a driver of a reset amplifier when the photodetector is being reset.

16. The circuit of claim 1, wherein the first column buffer further comprises:

a second switch transistor connected to the electronically reconfigurable transistor; and

a reset current source connected to the second switch transistor;

wherein during a reset operation, the second switch transistor connects the reset current source to the electronically reconfigurable transistor.

7. A CMOS imager array comprising a plurality of pixels, each pixel comprising:

a photodetector;

an access MOSFET having a source connected to the photodetector;

an amplifier MOSFET having a gate connected to a drain of the access MOSFET, a source connected to a signal bus, and a drain connected to a column buffer;

a reset MOSFET having a source connected to the drain of the access MOSFET, a drain connected to the column buffer, and a gate connected to a tapered reset signal generator; and

a distributed feedback amplifier comprising the amplifier MOSFET, the reset MOSFET and the column buffer to taper reset the photodetector, wherein the column buffer comprises;

a first switch transistor connected to drain of the reset MOSFET;

and

a second switch transistor connected to the drain of the amplifier MOSFET;

and

a reset current source connected to the second switch transistor;

wherein during a reset operation, the first and second switch transistors connect transistor connects the drain of the reset MOSFET with the drain of the amplifier MOSFET to form a feedback path, and the second switch transistor connects the reset current source to the amplifier MOSFET.

8. The imager array of claim 7, further comprising a row disable MOSFET having a source connected to the drain of the reset MOSFET and a drain connected to a row disable signal generator.

9. The imager array of claim 8, further comprising an access signal generator connected to the gate of the access MOSFET.

10. The imager array of claim 9, further comprising a second column buffer connected to the signal bus.

11. The imager array of claim 10, wherein the MOSFETs within each pixel are of identical polarity.

12. The imager array of claim 11, wherein the photodetector comprises a substrate diode with the silicide cleared.

13. An active pixel sensor circuit comprising:

a photodetector;

an access transistor connected to the photodetector;

an amplifier transistor, connected to an output of the access transistor and to a signal output bus;

a reset transistor connected between the access transistor and the amplifier transistor, wherein the reset transistor is reset with a tapered reset signal; and

a first column buffer connected to the amplifier transistor and to the reset transistor, the first column buffer comprising;

a first switch transistor connected to the reset transistor;

and

a second switch transistor connected to the amplifier transistor;

and

a reset current source connected to the second switch transistor;

wherein during a reset operation, the first and second switch transistors connect transistor connects the reset transistor with the amplifier transistor to form a feedback path, and the second switch transistor connects the reset current source to the amplifier transistor.

14. An imager array circuit comprising:

a first switch transistor connected to a first column bus;

a second switch transistor connected to a second column bus and the first switch transistor;

a reset current source connected to the second switch transistor;

a signal column bus; and

a plurality of pixel circuits connected to the first column bus, second column bus, and signal column bus, each pixel circuit comprising;

a photodetector;

an access transistor connected to the photodetector;

an amplifier transistor connected to the access transistor, the signal column bus and the second switch transistor; and

a reset transistor connected to the first column bus, the access transistor, and the amplifier transistor, wherein during a reset operation, the first switch transistor connects the reset transistor to the amplifier transistor to form a feedback path, and the second switch transistor connects the reset current source to the amplifier transistor.

15. The circuit of claim 14, wherein the amplifier transistor operates as a driver of a source follower amplifier when a signal from the photodetector is being read out, and operates as a driver of a reset amplifier when the photodetector is being reset.