Post passivation metal scheme for high-performance integrated circuit devices

• US RE43,674 E1
• Filed: 09/08/2006
• Issued: 09/18/2012
• Est. Priority Date: 10/18/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Lei, Ming-Ta, Huang, Ching-Cheng
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US11/518,595
• Time in Patent Office: 2,202 Days
• Field of Search: 438/618, 438/622, 438/625, 438/637, 438/642, 438/652, 438/669, 257/750, 257/758
• US Class Current: 438/618
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. No, or smaller ESD circuits are required due to the low impedance post-passivation interconnection, since any accumulated electrostatic discharge will be evenly distributed across all junction capacitance of the circuits on the chip. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal.

Claims

1. A post passivation interconnect structure, comprising:

one or more internal circuits comprising one or more active devices formed in and on a semiconductor substrate;

a fine line metallization system, formed over said semiconductor substrate in one or more thin layers of dielectric;

a passivation layer over said fine line metallization system;

a thick, wide metallization system formed above said passivation layer, wherein said thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein said thick, wide metallization system is connected to said one or more internal circuits; and

at least one wire-bondable bond pad created over said thick layers of dielectric, said at least one bond pad being connected with said thick, wide metallization system.

2. The interconnect structure of claim 1 wherein said distribution network is connected to said one or more internal circuits by vias, which are formed through said passivation layer, and through said one or more thin layers of dielectric.

3. The interconnect structure of claim 1 wherein said distribution network acts as a global distribution for said clock or signal voltages, and said vias are further connected to local clock or signal distribution networks, respectively, formed in said fine line metallization system.

4. The interconnect structure of claim 1 wherein said distribution network acts as a global distribution for said power and ground voltages, and said vias are further connected to local power and ground distribution networks, respectively, formed in said fine line metallization system.

5. The interconnect structure of claim 1 wherein metal in said thick, wide metallization system is greater than about 1 micrometer in thickness.

6. The interconnect structure of claim 1 wherein said thick, wide metallization system formed above said layer of passivation comprises one or more thick layers of dielectric, said thick layers of dielectric each having a thickness greater than about 2 micrometers.

7. A method for creating a post passivation interconnect structure, comprising:

providing one or more internal circuits comprising one or more active devices formed in and on a semiconductor substrate;

providing a fine line metallization system, formed over said semiconductor substrate in one or more thin layers of dielectric;

providing a passivation layer over said fine line metallization system;

providing a thick, wide metallization system formed above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein said thick, wide metallization system is connected to said one or more internal circuits; and

providing at least one wire-bondable bond pad created over said thick layers of dielectric, said at least one wire-bondable bond pad being connected with said thick, wide metallization system.

8. The method of claim 7 wherein said distribution network is connected to said one or more internal circuits by vias, which are formed through said one or more thick layers of dielectric, through said passivation layer, and through said one or more thin layers of dielectric.

9. The method of claim 7 wherein said distribution network acts as a global distribution for said clock or signal voltages, and said vias are further connected to local clock or signal distribution networks, respectively, formed in said fine line metallization system.

10. The method of claim 7 wherein said distribution network acts as a global distribution for said power and ground voltages, and said vias are further connected to local power and ground distribution networks, respectively, formed in said fine line metallization system.

11. The method of claim 7 wherein metal in said thick, wide metallization system is greater than about 1 micrometer in thickness.

12. The method of claim 7 wherein said thick, wide metallization system formed above said layer of passivation comprises one or more thick layers of dielectric, said thick layers of dielectric each having a thickness greater than about 2 micrometers.

13. The method of claim 7, wherein said providing at least one bond pad over said post-passivation interconnection structure comprises the steps of:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal including top metal being connected to said active devices having been provided over the substrate, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching an opening through the layer of passivation, this opening being aligned with a portion of said top metal, exposing top metal;

successively creating a first layer of metal comprising TiW over which a second layer metal comprising Au is created, preferably using the method of metal sputtering for the creation of these layers;

creating an exposure mask, preferably comprising photoresist, over the sputtered second layer of metal comprising Au, this mask exposing the second layer of metal over a surface area that is to form the low-resistance interconnection and the wire-bondable bond pad;

applying a bulk metal plating to the exposed surface of the second layer of metal comprising Au;

removing the exposure mask, and

etching the second layer of metal comprising Au and the first layer of metal comprising TiW in accordance with the plated layer of bulk metal, leaving in place the first and the second layers of metal where the bulk metal plating has been applied, thereby providing a metal system serving as both low-resistance conduction and wire-bonding pads.

14. The method of claim 13, with additional processing steps being performed prior to said successively creating a first layer of metal comprising TiW over which a second layer of metal comprising Au is created, said additional steps comprising:

depositing a first layer of dielectric, over said layer of passivation, including said opening created through said layer of passivation; and

patterning and etching the deposited first layer of dielectric, creating an opening through this first layer of dielectric, this opening being aligned with the opening that has been created through the layer of passivation.

15. The method of claim 13, said bulk metal being selected from the group consisting of Au and Al.

16. The method of claim 7, wherein said providing at least one bond pad over said post-passivation interconnection structure comprises the steps of:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal having been provided over the substrate, at least one layer of patterned top metal having been provided over the layer of fine-line interconnect metal, said at least one layer of patterned top metal having been connected to said layer of fine-line interconnect metal, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching at least one first opening through the layer of passivation, said at least one first opening being aligned with a portion of said at least one layer of top metal, exposing said at least one layer of top metal;

creating a first layer of metal, serving as a diffusion barrier and an adhesion layer, over said layer of passivation, preferably using metal sputtering for the creation of the first layer of metal;

creating an second layer of seed metal for subsequent processing of electroplating, preferably using methods of metal sputtering;

creating an exposure mask, preferably comprising photoresist, over the sputtered second layer of metal, said exposure mask exposing the second layer of metal over a surface area of the second layer of metal that is to form a low resistance interconnection;

applying a first metal plating to the exposed surface of the second layer of metal, creating a third layer of metal to form a low-resistance interconnection over the exposed surface area of the second layer of metal;

applying a second metal plating to the exposed surface of the third layer of metal, creating a fourth layer of metal to form a diffusion barrier over the surface area of the third layer of metal;

removing the exposure mask;

etching the first and second layers of metal in accordance with the applied third and fourth metal plating, thereby leaving in place the first, the second, the third and the fourth layers of metal that serve as diffusion barrier, electroplating seed layer, low-resistance layer and diffusion barrier respectively;

depositing a second layer of dielectric, preferable comprising polyimide, over the exposed surface of the fourth layer of metal and the exposed surface of said layer of passivation;

patterning and etching said deposited layer of dielectric, creating an opening through said layer of dielectric that aligns with a portion of the patterned and etched first, second, third and fourth layers of metal, exposing the fourth layer of metal; and

applying a third metal plating to the exposed surface of the fifth layer of metal, preferably using electroless plating, creating a bond pad.

17. The method of claim 16, said first layer of metal comprising an adhesive material between said first layer of dielectric and said second layer of metal.

18. The method of claim 17, said first layer of metal being selected from the group consisting of Cr and Ti and TiW.

19. The method of claim 16, said third layer of metal comprising a low-resistance metal.

20. The method of claim 19, said low-resistance metal being selected from the group consisting of Cu and Au and Al and W and Ag.

21. The method of claim 16, said first metal plating providing a protective surface over said layer of second layer of metal.

22. The method of claim 16, said fourth layer of metal comprising a metal serving as a diffusion barrier between said third layer of metal and said fifth layer of metal.

23. The method of claim 16, said third metal plating comprising Au plating.

24. The method of claim 7, wherein said providing at least one bond pad over said post-passivation interconnection structure comprises the steps of:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal having been provided over the substrate, at least one layer of patterned top metal having been provided over the layer of fine-line interconnect metal, said at least one layer of patterned top metal having been connected to said layer of fine-line interconnect metal, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching at least one first opening through the layer of passivation, said at least one first opening being aligned with a portion of said at least one layer of top metal, exposing said at least one layer of top metal;

creating a first layer of metal over said layer of passivation, preferably using the method of metal sputtering for the creation of this layer of metal;

sputtering a thin second layer over the first layer of metal, said second layer serving as a electroplating seed layer;

creating a exposure mask, preferably comprising photoresist, over the sputtered second layer of metal, said exposure mask exposing said second layer of metal over a surface area that is to serve as a low-resistance interconnection and a bond pad;

creating a third layer of metal over the exposed surface of the second layer of metal;

creating a fourth layer of metal over the exposed surface of the third layer of metal;

creating a fifth layer of metal over the exposed surface of the fourth layer of metal;

removing the exposure mask;

etching the first and the second layers of metal in accordance with the created fifth layer of metal, leaving in place the first, second, third, fourth and fifth layers of metal where the fifth layer of metal has been applied, these layers serving as a low-resistance interconnection and a bond pad, exposing the fifth layer of metal, further exposing the layer of passivation;

depositing a layer of dielectric, preferable comprising polyimide, over the exposed surface of the fifth layer of metal and the exposed surface of the layer of dielectric of passivation;

patterning and etching the deposited second layer of dielectric, creating an opening through the second layer of dielectric that aligns with a portion of the patterned and etched first, second, third, fourth and fifth layers of metal, exposing the fifth layer of metal, creating a bond pad.

25. The method of claim 24, said first layer of metal comprising a layer of adhesion material between said passivation layer and said third layer of metal.

26. The method of claim 25, said adhesion material comprising a metal being selected from the group consisting of Cr and Ti and TiW.

27. The method of claim 24 said thin second layer of metal comprising a seed layer for electroplating of said third layer of metal.

28. The method of claim 27, said seed layer preferably comprising copper.

29. The method of claim 24 said third layer of metal preferably comprising a low-resistance metal.

30. The method of claim 29, said low-resistance metal being selected from the group consisting of Cu and Au and Al and Ag and W.

31. The method of claim 24, said fourth layer of metal providing a layer serving as surface protection for said third layer of metal and a diffusion barrier between said third layer of metal and said fifth layer of metal.

32. The method of claim 31 said fourth layer of surface protection comprising Ni.

33. The method of claim 24, said fifth layer of metal comprising a wire-bondable metal.

34. The method of claim 33 said wire-bondable metal comprising a metal selected from the group consisting of Au and Al.

35. The method of claim 7, wherein said providing at least one bond pad over said post-passivation interconnection structure comprises the steps of:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal having been provided over the substrate, at least one layer of patterned top metal having been provided over the layer of fine-line interconnect metal, said at least one layer of patterned top metal having been connected to said layer of fine-line interconnect metal, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching at least one first opening through the layer of passivation, said at least one first opening being aligned with a portion of said at least one layer of top metal, exposing said at least one layer of top metal;

depositing a first layer of dielectric over said layer of passivation, including at least one opening created through said layer of passivation, said first layer of dielectric preferably comprising polyimide;

patterning and etching the deposited first layer of dielectric, creating at least one second opening through this first layer of dielectric, said at least one second opening being aligned with said at least one first opening through the layer of passivation;

creating a layer of metal over said first layer of dielectric including inside surfaces of said second opening created through said first layer of dielectric, preferably using the method of metal sputtering for the creation of this layer of metal;

creating an exposure mask, preferably comprising photoresist, over the sputtered layer of metal, said exposure mask covering this layer over a surface area of the metal layer that is to serve as a low-resistance interconnection and a bond pad;

etching the layer of metal in accordance with the exposure mask, exposing said first layer of dielectric;

removing the exposure mask, exposing said layer of metal;

depositing a second layer of dielectric, preferable comprising polyimide, over the exposed surface of the fourth layer of metal and the exposed surface of the first layer of dielectric; and

patterning and etching the deposited second layer of dielectric, creating an opening through the second layer of dielectric that aligns with a portion of the patterned and etched layer of metal, exposing the layer of metal, the exposed surface of the layer of metal serving as a bond pad.

36. The method of claim 35, said layer of metal comprising aluminum.

37. The method of claim 13, whereby first layer of metal comprises a metal selected from the group consisting of adhesion and diffusion barrier metals.

38. The method of claim 14, said first layer of dielectric comprising a polymer.

39. The method of claim 14, said first layer of dielectric comprising a material selected from the group consisting of polyimide and silicon elastomer and benzocyclobutane.

40. The method of claim 16, additionally providing prior to said step of creating a first layer of metal over said layer of passivation the steps of:

depositing a first layer of dielectric over said layer of passivation, including the at least one first opening created through said layer of passivation, said first layer of dielectric preferably comprising polyimide; and

patterning and etching the deposited first layer of dielectric, creating at least one second opening through this first layer of dielectric, said at least one second opening being aligned with said at least one first opening through the layer of passivation.

41. The method of claim 17, said second layer of metal comprising a metal serving as an electroplating seed layer for subsequent electroplating of said third layer of metal.

42. The method of claim 17, said second layer of metal comprising copper.

43. The method of claim 7, wherein said providing at least one bond pad over said post-passivation interconnection structure comprises the steps of:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal having been provided over the substrate, at least one layer of patterned top metal having been provided over the layer of fine-line interconnect metal, said at least one layer of patterned top metal having been connected to said layer of fine-line interconnect metal, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching at least one first opening through the layer of passivation, said at least one first opening being aligned with a portion of said at least one layer of top metal, exposing said at least one layer of top metal;

creating a layer of metal over said passivation layer, preferably using the method of metal sputtering for the creation of this layer of metal;

creating an exposure mask, preferably comprising photoresist, over the sputtered layer of metal, said exposure mask covering this layer over a surface area of the metal layer that is to serve as a low-resistance interconnection and a bond pad;

etching the layer of metal in accordance with the exposure mask, exposing said layer of passivation;

removing the exposure mask, exposing said layer of metal;

depositing a layer of dielectric, preferably comprising polyimide, over the exposed surface of said layer of metal and the exposed surface of the layer of passivation; and

patterning and etching the deposited layer of dielectric, creating an opening through the layer of dielectric that aligns with a portion of the patterned and etched layer of metal, exposing the layer of metal, the exposed surface of the layer of metal serving as a bond pad.

53. The method of claim 7, wherein said providing at least one bond pad over said post-passivation interconnection structure comprises the steps of:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal including at least one layer of top metal being connected to said active devices having been provided over the substrate, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching at least one first opening through the layer of passivation, said at least one first opening being aligned with a portion of said at least one layer of top metal, exposing said at least one layer of top metal;

depositing a first layer of dielectric, preferably comprising polyimide;

patterning and etching the deposited first layer of dielectric, creating at least one second opening through this first layer of dielectric, said at least one second opening being aligned with said at least one first opening created through the layer of passivation;

creating a first layer of metal over said first layer of dielectric including inside surfaces of said at least one second opening created through said first layer of dielectric;

patterning said first layer of metal, creating at least one pattern of said first layer of metal contacting said at least one layer of top metal;

depositing a second layer of dielectric over said first layer of dielectric, including said at least one pattern of said first layer of metal;

creating at least one third opening through the second layer of dielectric, said at least one third opening being aligned with a portion of said at least one pattern of said first layer of metal;

creating a second layer of metal over said second layer of dielectric including inside surfaces of said at least one third opening created through said second layer of dielectric;

patterning said second layer of metal, creating at least one pattern of said second layer of metal contacting said at least one pattern of first layer of metal;

depositing a third layer of dielectric over said second layer of dielectric, including said at least one pattern of said second layer of metal;

creating at least one fourth opening through the third layer of dielectric, said at least one fourth opening being aligned with a portion of said at least one pattern of said second layer of metal, exposing said at least one pattern of said second layer of metal.

54. The method of claim 53, wherein said first layer of metal comprising a low-resistance metal.

55. The method of claim 54, said low-resistance metal being selected from the group consisting of Cu and Au and Al and W and Ag.

56. The method of claim 53, wherein said second layer of metal comprising a first layer of low-resistance metal over which a second layer of wire-bondable material is deposited.

57. The method of claim 56, said low-resistance metal being selected from the group consisting of Cu and Au and Al and W and Ag.

58. The method of claim 56, said wire-bondable material being selected from the group consisting of Au and Al.

59. The method of claim 53, additionally providing an adhesive layer between said first layer of dielectric and said first layer of metal.

60. The method of claim 53, additionally providing a protective layer of said first layer of metal.

61. The method of claim 53, additionally providing an adhesive layer between said second layer of dielectric and said second layer of metal.

62. The method of claim 53, additionally providing a protective layer of said second layer of metal.

63. The method of claim 24 additionally providing prior to said step of creating a first layer of metal over said first layer of dielectric the steps of:

depositing a first layer of dielectric over said layer of passivation, including the at least one opening created through said layer of passivation, said first layer of dielectric preferably comprising polyimide; and

patterning and etching the deposited first layer of dielectric, creating at least one second opening through this first layer of dielectric, said at least one second opening being aligned with said at least one first opening through the layer of passivation.

64. The method of claim 7, wherein said providing at least one bond pad over said post-passivation interconnection structure comprises the steps of:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal including top metal being connected to said active devices having been provided over the substrate, said top metal comprising wire-bondable metal, said top metal comprising at least one first portion of top metal comprising a bond pad, said top metal further comprising at least one second portion of top metal that needs to be connected to said first portion of top metal, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching a first, second and third opening through the layer of passivation, said first opening being aligned with a portion of said first portion of top metal, said second opening being aligned with a portion of said first portion of top metal, said third opening being aligned with a portion of said second portion of top metal, exposing said first and second portion of top metal;

creating a first layer of metal over said passivation layer, creating a second layer of metal serving as a seed layer over said first layer of metal;

creating an exposure mask, preferably comprising photoresist, over the created second layer of metal, exposing the second layer of metal only over the surface area of the second layer of metal at least on the region over and between said second and third opening, and not exposing said first opening;

creating a patterned third layer of metal over the exposed surface of the second layer of metal;

creating a patterned fourth layer of metal over the patterned third layer of metal;

removing the exposure mask, exposing the second layer of metal, leaving in place a mask of the patterned third and fourth layers of metal in place overlying the second layer of metal;

etching the second and the first layers of metal in accordance with the mask of third and fourth layers of metal overlying the second and third layers of metal, thereby avoiding etch damage to said top metal in said bond pad, thereby exposing the passivation layer;

depositing a layer of dielectric over the patterned fourth layer of metal and the layer of passivation, preferably comprising polyimide; and

patterning and etching the deposited layer of dielectric, creating an opening through the layer of dielectric that aligns with said bond pad.

65. The method of claim 7, wherein said providing at least one bond pad over said post-passivation interconnection structure comprises the steps of:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal including at least one layer of top metal being connected to said active devices having been provided over the substrate, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching at least one first opening through the layer of passivation, said at least one first opening being aligned with a portion of said at least one layer of top metal, exposing said at least one layer of top metal;

creating a first layer of metal over said passivation layer;

patterning said first layer of metal, creating at least one pattern of said first layer of metal contacting said at least one layer of top metal;

depositing a first layer of dielectric over said layer of passivation, including said at least one pattern of said first layer of metal;

creating at least one third opening through the first layer of dielectric, said at least one third opening being aligned with a portion of said at least one pattern of said first layer of metal;

creating a second layer of metal over said first layer of dielectric including inside surfaces of said at least one third opening created through said first layer of dielectric;

patterning said second layer of metal, creating at least one pattern of said second layer of metal contacting said at least one pattern of first layer of metal;

depositing a second layer of dielectric over said first layer of dielectric, including said at least one pattern of said second layer of metal;

creating at least one fourth opening through the second layer of dielectric, said at least one fourth opening being aligned with a portion of said at least one pattern of said second layer of metal, exposing said at least one pattern of said second layer of metal.

44. A method for creating a post passivation interconnect structure, comprising:

providing a substrate, active devices having been created in or on the substrate, a layer of fine-line interconnect metal including top metal being connected to said active devices having been provided over the substrate, said top metal comprising wire-bondable metal, said top metal comprising at least one first portion of top metal which comprises a bond pad, said top metal further comprising at least one second portion of top metal that needs to be connected to said first portion of top metal, a layer of passivation having been provided over the layer of fine-line interconnect metal;

patterning and etching a first, second and a third opening through the layer of passivation, said first opening being aligned with a portion of said first portion of top metal, said second opening being aligned with a portion of said first portion of top metal, said third opening being aligned with a portion of said second portion of top metal, exposing said first and second portion of top metal;

depositing a first layer of dielectric, preferably comprising polyimide, over said layer of passivation, including said first, second and third openings created in said layer of passivation;

patterning and etching the deposited first layer of dielectric, creating a fourth, a fifth and a sixth openings through said first layer of dielectric, said fourth opening through said first layer of dielectric being aligned with said first opening created through said layer of passivation, said fifth and sixth openings through said first layer of dielectric respectively being aligned with said second and third openings created through the layer of passivation;

creating a first layer metal over said first layer of dielectric, creating a second layer of metal serving as seed layer over said first layer of metal;

creating an exposure mask, preferably comprising photoresist, over the created second layer of metal, exposing the second layer of metal only over the surface area of the second layer of metal at least in a region over and between said second and third opening while not exposing said first opening;

creating a patterned third layer of metal over the exposed surface of the second layer of metal;

creating a patterned fourth layer of metal over the patterned third layer of metal;

removing the exposure mask, exposing the second layer of metal, leaving in place a mask of the patterned third and fourth layers of metal in place overlying the second layer of metal;

etching the second and the first layers of metal in accordance with the masking of third and fourth layers of metal overlying these second and first layers of metal, through selection of an etchant to avoid etch damage to said top metal in said bond pad, thereby exposing said bond pad and a portion of said passivation layer and said first layer of dielectric;

depositing a second layer of dielectric over the patterned fourth layer of metal and the first layer of dielectric, preferably comprising polyimide; and

patterning and etching the deposited second layer of dielectric, creating an opening through the second layer of dielectric that aligns with said bond pad.

45. The method of claim 44, said first layer of metal providing an adhesion layer between said first layer of dielectric and said second layer of metal in addition to providing a diffusion barrier metal between said top metal and said second and third layer of metal.

46. The method of claim 45, said adhesion layer comprising a material selected from the group consisting of Ti and Cr and TiW.

47. The method of claim 44, said second layer of metal comprising a seed layer for said third layer of metal.

48. The method of claim 47, said second layer of metal comprising Cu.

49. The method of claim 44, said patterned third layer of metal comprising a low-resistance metal.

50. The method of claim 49, said low-resistance metal comprising an element selected from the group consisting of Cu and Au and Al and W and Ag.

51. The method of claim 44, said patterned fourth layer of metal comprising a protective metal for the third layer of metal.

52. The method of claim 51, said protective metal comprising Ni.

66. A method of forming post passivation interconnect structure, comprising:

providing one or more internal circuits comprising one or more active devices formed in and on a semiconductor substrate;

providing a fine line metallization system, formed over said semiconductor substrate in one or more thin layers of dielectric;

providing a passivation layer over said fine line metallization system;

providing a thick, wide metallization system formed above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein said thick, wide metallization system is connected to said one or more internal circuits; and

providing at least one wire-bondable bond pad adjacent to said thick layers of dielectric, said at least one wire-bondable bond pad being connected with said thick, wide metallization system.

67. The method of claim 66 wherein said at least one wire-bondable bond pad is formed from a top layer of said fine line metallization system.

68. The method of claim 67 wherein said at least one wire-bondable bond pad is exposed through said passivation layer.

69. The method of claim 66 wherein said at least one wire-bondable bond pad is connected to said thick, wide metallization system through said fine line metallization system and through openings in said passivation layer.

70. A chip comprising:

a silicon substrate;

an active device in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a metal layer over said silicon substrate;

a passivation layer on said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metal layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metal layer, and said second contact point is at a bottom of said second opening;

a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point; and

a metallization structure on said polymer layer and said first and second contact points, wherein said metallization structure is connected to said first contact point through said third opening and connected to said second contact point through said fourth opening, wherein said first contact point is connected to said second contact point through said metallization structure, wherein said metallization structure comprises an adhesion layer on said polymer layer and said first and second contact points, a copper-containing seed layer over said adhesion layer, and an electroplated copper layer over said copper-containing seed layer, wherein said adhesion layer is under said electroplated copper layer, but is not at a sidewall of said electroplated copper layer.

71. The chip of claim 70, wherein said adhesion layer comprises a titanium-containing layer.

72. The chip of claim 70, wherein said adhesion layer comprises a chromium-containing layer.

73. The chip of claim 70, wherein said metallization structure further comprises a nickel-containing layer on said electroplated copper layer.

74. The chip of claim 70, wherein said metal layer comprises aluminum.

75. The chip of claim 70, wherein said polymer layer comprises polyimide.

76. The chip of claim 70, wherein said metallization structure is configured for connection to an external circuit by wirebonding.

91. The chip of claim 70, wherein said metallization structure is configured for connection to an external circuit by solder bonding.

77. A chip comprising:

a silicon substrate;

an active device in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a metal layer over said silicon substrate;

a passivation layer on said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metal layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metal layer, and said second contact point is at a bottom of said second opening;

an interconnecting structure over said passivation layer and on said first and second contact points, wherein said interconnecting structure is connected to said first contact point through said first opening and connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein no polymer layer is between said passivation layer and said interconnecting structure, wherein said interconnecting structure comprises an adhesion layer over said passivation layer and on said first and second contact points, a copper-containing seed layer over said adhesion layer, and an electroplated copper layer over said copper-containing seed layer, wherein said adhesion layer is under said electroplated copper layer, but is not at a sidewall of said electroplated copper layer; and

a polymer layer over said interconnecting structure and said passivation layer, wherein said polymer layer covers a top surface and a sidewall of said interconnecting structure.

78. The chip of claim 77, wherein said adhesion layer comprises a titanium-containing layer.

79. The chip of claim 77, wherein said adhesion layer comprises a chromium-containing layer.

80. The chip of claim 77, wherein said interconnecting structure further comprises a nickel-containing layer over said electroplated copper layer, wherein said nickel-containing layer is connected to said first and second contact points through said electroplated copper layer.

81. The chip of claim 77, wherein said metal layer comprises aluminum.

82. The chip of claim 77, wherein said polymer layer comprises polyimide.

83. The chip of claim 77, wherein said interconnecting structure is configured for connection to an external circuit by wirebonding.

92. The chip of claim 77, wherein said interconnecting structure is configured for connection to an external circuit by solder bonding.

84. A chip comprising:

a silicon substrate;

an active device in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a metal layer over said silicon substrate;

a passivation layer on said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metal layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metal layer, and said second contact point is at a bottom of said second opening;

a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first contact point, and a fourth opening in said first polymer layer is over said second contact point;

an interconnecting structure on said first polymer layer and said first and second contact points, wherein said interconnecting structure is connected to said first contact point through said third opening and connected to said second contact point through said fourth opening, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein said interconnecting structure comprises an adhesion layer on said first polymer layer and said first and second contact points, a copper-containing seed layer over said adhesion layer, and an electroplated copper layer over said copper-containing seed layer, wherein said adhesion layer is under said electroplated copper layer, but is not at a sidewall of said electroplated copper layer; and

a second polymer layer on said interconnecting structure and said first polymer layer, wherein said second polymer layer covers a top surface and a sidewall of said interconnecting structure.

85. The chip of claim 84, wherein said adhesion layer comprises a titanium-containing layer.

86. The chip of claim 84, wherein said adhesion layer comprises a chromium-containing layer.

87. The chip of claim 84, wherein said interconnecting structure further comprises a nickel-containing layer over said electroplated copper layer, wherein said nickel-containing layer is connected to said first and second contact points through said electroplated copper layer.

88. The chip of claim 84, wherein said metal layer comprises aluminum.

89. The chip of claim 84, wherein said second polymer layer comprises polyimide.

90. The chip of claim 84, wherein said interconnecting structure is configured for connection to an external circuit by wirebonding.

93. The chip of claim 84, wherein said interconnecting structure is configured for connection to an external circuit by solder bonding.

94. A chip comprising:

a silicon substrate;

an active device in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first metal layer over said silicon substrate;

a separating layer on said dielectric layer, wherein a first opening in said separating layer is over a first contact point of said first metal layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said first metal layer, and said second contact point is at a bottom of said second opening;

an interconnecting layer over said separating layer and on said first and second contact points, wherein said interconnecting layer is connected to said first contact point through said first opening and connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said interconnecting layer, wherein no polymer layer is between said separating layer and said interconnecting layer, wherein said interconnecting layer comprises an adhesion layer over said separating layer and on said first and second contact points, and a second metal layer over said adhesion layer, wherein said adhesion layer is under said second metal layer, but is not at a sidewall of said second metal layer; and

a polymer layer over said interconnecting layer and said separating layer, wherein said polymer layer covers a top surface and a sidewall of said interconnecting layer wherein no opening in said polymer layer is over said interconnecting layer.

95. The chip of claim 94, wherein said adhesion layer comprises a titanium-containing layer.

96. The chip of claim 94, wherein said second metal layer comprises a copper layer over said adhesion layer, and a nickel-containing layer over said copper layer, wherein said nickel-containing layer is connected to said first and second contact points through said copper layer.

97. The chip of claim 94, wherein said first metal layer comprises aluminum.

98. The chip of claim 94, wherein said second metal layer comprises copper.

99. A chip comprising:

a silicon substrate;

an active device in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metal layer over said silicon substrate and in said first dielectric layer, wherein said metal layer comprises a damascene metal;

a passivation layer on said first dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metal layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metal layer, and said second contact point is at a bottom of said second opening;

an interconnecting structure on said passivation layer and said first and second contact points, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein said interconnecting structure comprises a first adhesion layer and a first copper layer over said first adhesion layer, wherein said interconnecting structure has a top surface at a horizontal level;

a second dielectric layer on said top surface and over said passivation layer, wherein a third opening in said second dielectric layer is over a third contact point of said interconnecting structure, and said third contact point is at a bottom of said third opening, wherein said third contact point is connected to said first contact point through said first opening, and said third contact point is connected to said second contact point through said second opening, wherein said second dielectric layer comprises a polymer layer over said top surface and across an edge of said interconnecting structure, wherein said polymer layer comprises a first portion over said horizontal level and a second portion under said horizontal level, wherein said second dielectric layer covers said top surface and a sidewall of said interconnecting structure; and

a metallization structure on said polymer layer and said third contact point, wherein said metallization structure is connected to said third contact point through said third opening, wherein said metallization structure comprises a second adhesion layer and a second copper layer over said second adhesion layer.

100. The chip of claim 99, wherein said first adhesion layer comprises a chromium-containing layer.

101. The chip of claim 99, wherein said second adhesion layer comprises a chromium-containing layer.

102. The chip of claim 99, wherein said metallization structure further comprises a nickel-containing layer over said second copper layer.

103. The chip of claim 99, wherein said interconnecting structure further comprises a nickel-containing layer over said first copper layer.

104. The chip of claim 99, wherein said metallization structure is configured for connection to an external circuit by wirebonding.

105. The chip of claim 99 further comprising a third dielectric layer on said metallization structure and said polymer layer.

106. A chip comprising:

a silicon substrate;

an active device in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a metal layer over said silicon substrate and in said dielectric layer, wherein said metal layer comprises a damascene metal, wherein said metal layer has a first top surface with a first region, a second region and a third region between said first and second regions, wherein said first top surface is substantially coplanar with a second top surface of said dielectric layer;

a passivation layer on said first and second regions and said second top surface, wherein a first opening in said passivation layer is over said third region, and said third region is at a bottom of said first opening;

a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said third region; and

a metallization structure over said silicon substrate, wherein said metallization structure is connected to said third region through said second opening, wherein said metallization structure comprises an aluminum layer having a thickness greater than 1 micrometer.

107. The chip of claim 106, wherein said metallization structure is configured for connection to an external circuit by wirebonding.

108. The chip of claim 106 further comprising a second polymer layer on said first polymer layer and over said metallization structure.

109. The chip of claim 106 further comprising a second polymer layer on said first polymer layer and over said metallization structure, wherein a third opening in said second polymer layer is over a fourth region of said metallization structure, and said fourth region is at a bottom of said third opening, wherein said fourth region is connected to said third region through said second opening, wherein said fourth region is not vertically over said third region, wherein said fourth region is configured for wirebonding.

110. The chip of claim 106, wherein said metallization structure is configured for connection to an external circuit by solder bonding.

111. The chip of claim 106, wherein said first polymer layer has a thickness greater than 2 micrometers.

112. The chip of claim 106, wherein said first polymer layer comprises polyimide.

113. A chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

an interconnecting structure in said first dielectric layer, wherein said interconnecting structure comprises a damascene metal;

a separating layer over said first dielectric layer, wherein multiple first vias are in said separating layer;

an interconnect over said separating layer, wherein said interconnect comprises an aluminum layer, wherein said multiple first vias are connected to each other through said interconnect; and

a second dielectric layer over said separating layer, wherein said second dielectric layer has a portion over said interconnect, wherein a second via in said portion is vertically over said interconnect and one of said multiple first vias.

114. The chip of claim 113, wherein said interconnect comprises a power interconnect.

115. The chip of claim 113, wherein said interconnect comprises a ground interconnect.

116. The chip of claim 113, wherein said aluminum layer has a thickness greater than 1 micrometer.

117. The chip of claim 113, wherein no polymer layer is between said separating layer and said interconnect.

118. The chip of claim 113, wherein said second dielectric layer comprises a polymer.

119. The chip of claim 113, wherein the number of said multiple first vias is at least ten.