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Post passivation metal scheme for high-performance integrated circuit devices

  • US RE43,674 E1
  • Filed: 09/08/2006
  • Issued: 09/18/2012
  • Est. Priority Date: 10/18/2000
  • Status: Expired due to Term
First Claim
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1. A post passivation interconnect structure, comprising:

  • one or more internal circuits comprising one or more active devices formed in and on a semiconductor substrate;

    a fine line metallization system, formed over said semiconductor substrate in one or more thin layers of dielectric;

    a passivation layer over said fine line metallization system;

    a thick, wide metallization system formed above said passivation layer, wherein said thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein said thick, wide metallization system is connected to said one or more internal circuits; and

    at least one wire-bondable bond pad created over said thick layers of dielectric, said at least one bond pad being connected with said thick, wide metallization system.

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