MPGA products based on a prototype FPGA
First Claim
1. An integrated circuit design platform, comprising:
- a field programmable gate array (FPGA) prototype device comprised of;
a circuits layout comprising a plurality of field programmable logic blocks and a plurality of layers of field programmable interconnects; and
a set of input/output pad structures; and
a first region within the circuits layout, said region having registers at one or more boundaries of the region, said registers capable of coupling to said input/output pad structures; and
a metal programmable gate array (MPGA) production device fabricated separately from the FPGA prototype device, the MPGA production device comprised of;
a substantially identical circuit layout as in the first region of the FPGA; and
a substantially identical layout of one or more layers of programmable interconnects as in the first region of the FPGA;
wherein, a design mapped to the first region of the FPGA is identically mapped to the MPGA.
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Accused Products
Abstract
A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.
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Citations
31 Claims
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1. An integrated circuit design platform, comprising:
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a field programmable gate array (FPGA) prototype device comprised of; a circuits layout comprising a plurality of field programmable logic blocks and a plurality of layers of field programmable interconnects; and a set of input/output pad structures; and a first region within the circuits layout, said region having registers at one or more boundaries of the region, said registers capable of coupling to said input/output pad structures; and a metal programmable gate array (MPGA) production device fabricated separately from the FPGA prototype device, the MPGA production device comprised of; a substantially identical circuit layout as in the first region of the FPGA; and a substantially identical layout of one or more layers of programmable interconnects as in the first region of the FPGA; wherein, a design mapped to the first region of the FPGA is identically mapped to the MPGA. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit design platform, comprising:
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a prototype field programmable (FPGA) device comprising a layout of electronic circuits and input/output pads; and a production mask programmable (MPGA) device fabricated separately from the FPGA prototype device, the MPGA device comprising; a layout of electronic circuits substantially identical to a region within the prototype FPGA device; and a subset of input/output pads as within the prototype FPGA device; wherein a design placed and routed within the region of the prototype FPGA device using the subset of input/output pads as in the production MPGA device, is identically placed and routed in the production MPGA device. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A small mask programmable gate array (MPGA) device derived from a large field programmable gate array (FPGA) device fabricated separately from the FPGA prototype device, the MPGA device, comprising:
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a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA device; and input/output pads matching a subset of the input/output pads of the FPGA device; wherein, a design that is mapped to said small region of the FPGA device using said subset of input/output pads by a user programmable means is identically mapped to the MPGA device by a hard-wire circuit during a subsequent fabrication of the MPGA device. - View Dependent Claims (19, 20)
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21. A method of producing a metal programmable gate array (MPGA), said method comprising:
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accessing a design for a circuits layout for a field programmable gate array (FPGA), said circuits layout in said design comprising a plurality of field programmable logic blocks configured in a core region, said core region in said design comprising a plurality of sub-regions that are smaller than said core region, said design for said FPGA further comprising a first region within said circuits layout and a register at a boundary of said first region, a plurality of layers of field programmable interconnects, and a set of input/output (I/O) pad structures; and fabricating an MPGA device based on said design, said design configured so that said fabricating of said MPGA device is separate from fabrication of an FPGA according to said design, said MPGA device comprising a circuit layout comprising a subset of said plurality of said sub-regions that are in said design, said circuit layout of said MPGA device comprising a substantially identical layout as in said first region of said design but excluding said register at said boundary of said first region, wherein said MPGA device further comprises a substantially identical layout of one or more of said layers of programmable interconnects as in said first region of said design; wherein said first region in said design is identically mapped to said MPGA device. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification