MPGA products based on a prototype FPGA

• US RE45,110 E1
• Filed: 03/02/2012
• Issued: 09/02/2014
• Est. Priority Date: 03/20/2006
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Yakimishu Co Ltd LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya, Suaris, Peter Ramyalal, White, Thomas Henry
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US13/411,486
• Time in Patent Office: 914 Days
• Field of Search: 716/116, 716/117, 716/128, 716/138, 326 37- 41
• US Class Current: 716/138
• CPC Class Codes: G06F 17/5045 Circuit design G06F17/5068 takes precedence; logic circuits H03K19/00
• CPC Class Codes: G06F 17/5054 for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 27/1052 Memory structures and multistep manufacturing processes therefor not provided for in groups H01L27/1055 - H01L27/112
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.

Claims

1. An integrated circuit design platform, comprising:

a field programmable gate array (FPGA) prototype device comprised of;

a circuits layout comprising a plurality of field programmable logic blocks and a plurality of layers of field programmable interconnects; and

a set of input/output pad structures; and

a first region within the circuits layout, said region having registers at one or more boundaries of the region, said registers capable of coupling to said input/output pad structures; and

a metal programmable gate array (MPGA) production device fabricated separately from the FPGA prototype device, the MPGA production device comprised of;

a substantially identical circuit layout as in the first region of the FPGA; and

a substantially identical layout of one or more layers of programmable interconnects as in the first region of the FPGA;

wherein, a design mapped to the first region of the FPGA is identically mapped to the MPGA.

2. The platform of claim 1, wherein the FPGA comprises a configuration circuit to field program the programmable logic blocks and programmable interconnects.

3. The platform of claim 2, wherein in the FPGA, the transistors for logic circuits are formed on a first module layer and the configuration circuit is formed on a second module layer positioned substantially above or below the first module layer.

4. The platform of claim 2, wherein the configuration circuit comprises one or more of:

resistor, capacitor, SRAM cell, DRAM cell, Flash cell, EPROM cell, EEPROM cell, Carbon nano-tube, resistance modulating element, ferro-electric element, electro-chemical cell, electro-mechanical element, optical element and electro-magnetic cell.

5. The platform of claim 1, wherein the MPGA comprises a customized metal circuit to mask program the programmable logic blocks and programmable interconnects.

6. The platform of claim 5, wherein the customized metal circuit comprises one or more of:

wire connection, wire disconnect, via connection, resistor element, shorted capacitor, capacitor, power bus connection, ground bus connection, transistor short, logic zero output connection, and logic one output connection.

7. The platform of claim 1, wherein said first region of the FPGA and said first MPGA further comprises comprise a substantially identical layout of one or more pass-gate devices to couple said programmable logic block to said an interconnect wire, wherein:

in the FPGA, the pass-gate device couples the logic block to the interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising;

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the MPGA, the pass-gate device couples the logic block to the interconnect wire, said pass-gate device controlled by an output of a ROM bit, said ROM bit comprising;

a metal connection to a power bus to couple the logic block to the interconnect wire; and

a metal connection to a ground bus to decouple the logic block from the interconnect wire.

8. The platform of claim 1, wherein said first region of the FPGA and said first MPGA further comprises comprise a substantially identical layout of one or more pass-gate devices to couple said one or more logic blocks to said an interconnect wire, wherein:

in the FPGA, a pass-gate device couples a logic block to an interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising;

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the MPGA, said pass-gate device is decoupled from said interconnect wire when the RAM bit comprises a logic zero;

wherein an interconnect wire in the FPGA comprises a high capacitance due to the pass-gate device junctions coupled to the interconnect wire, and wherein said interconnect wire in the MPGA comprises less capacitance due to the pass-gate junctions decoupled from the interconnect wire.

9. The platform of claim 1, wherein said first region of the FPGA and said first MPGA further comprises comprise a substantially identical layout of one or more pass-gate devices to couple said one or more logic blocks to a said an interconnect wire, wherein:

in the FPGA, a pass-gate device couples a logic block to an said interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising;

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the MPGA, said pass-gate device is replaced by a metal jumper when the RAM bit comprises a logic one;

wherein an interconnect wire coupled to a logic block encounters a high resistance from the on pass-gate device in the FPGA, and wherein said interconnect wire coupled to the logic block in the MPGA encounters less resistance due to the metal-jumper.

10. The platform of claim 1, further comprising:

said field programmable gate array (FPGA) prototype device comprised of;

a second region within the circuits layout, said second region having registers at one or more boundaries of the region, said register registers capable of coupling to said input/output pad structure; and

a second metal programmable gate array (second MPGA) production device comprised of;

a substantially identical circuits layout as in the second region of the FPGA; and

a substantially identical layout of one or more layers of programmable interconnects as in the second region of the FPGA;

wherein, a design mapped to the second region of the FPGA is identically mapped to the second MPGA.

11. An integrated circuit design platform, comprising:

a prototype field programmable (FPGA) device comprising a layout of electronic circuits and input/output pads; and

a production mask programmable (MPGA) device fabricated separately from the FPGA prototype device, the MPGA device comprising;

a layout of electronic circuits substantially identical to a region within the prototype FPGA device; and

a subset of input/output pads as within the prototype FPGA device;

wherein a design placed and routed within the region of the prototype FPGA device using the subset of input/output pads as in the production MPGA device, is identically placed and routed in the production MPGA device.

12. The platform of claim 11, wherein the region of the FPGA and the MPGA has substantially identical layouts of transistors and substantially identical layouts of one or more layers of interconnects.

13. The platform of claim 11, wherein the MPGA has at least one customized interconnect layer to map field programmable data in the prototype FPGA to mask programmable data.

14. The platform of claim 11, wherein the FPGA comprises a configuration circuit further comprising one or more of:

resistor, capacitor, SRAM cell, DRAM cell, Flash cell, EPROM cell, EEPROM cell, Carbon nano-tube, resistance modulating element, ferro-electric element, electro-chemical cell, electro-mechanical element, optical element and electromagnetic cell.

15. The platform of claim 11, wherein the MPGA comprises a customized metal circuit further comprising one or more of:

wire connection, wire disconnect, via connection, resistor element, shorted capacitor, capacitor, power bus connection, ground bus connection, transistor short, logic zero output connection, and logic one output connection.

16. The platform of claim 11, wherein the FPGA comprises a RAM bit, and wherein the MPGA comprises a hard-wired ROM bit.

17. The platform of claim 11, wherein the MPGA comprises one or more of:

a metal link to couple a node to a power supply voltage; and

a metal link to couple a node to a ground supply voltage; and

a metal jumper to short two nodes; and

a metal disconnect to isolate two nodes.

18. A small mask programmable gate array (MPGA) device derived from a large field programmable gate array (FPGA) device fabricated separately from the FPGA prototype device, the MPGA device, comprising:

a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA device; and

input/output pads matching a subset of the input/output pads of the FPGA device;

wherein, a design that is mapped to said small region of the FPGA device using said subset of input/output pads by a user programmable means is identically mapped to the MPGA device by a hard-wire circuit during a subsequent fabrication of the MPGA device.

19. The device of claim 18, further comprising:

a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and

a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.

20. The device of claim 18, wherein:

a first set of input/output pad pads to a first set of logic blocks within the MPGA is identically mapped from that of the FPGA; and

a second set of input/output pad pads to a second set of logic blocks within the MPGA is mapped from the corresponding logic blocks to registers at region boundary to corresponding input/output pads of the FPGA.

21. A method of producing a metal programmable gate array (MPGA), said method comprising:

accessing a design for a circuits layout for a field programmable gate array (FPGA), said circuits layout in said design comprising a plurality of field programmable logic blocks configured in a core region, said core region in said design comprising a plurality of sub-regions that are smaller than said core region, said design for said FPGA further comprising a first region within said circuits layout and a register at a boundary of said first region, a plurality of layers of field programmable interconnects, and a set of input/output (I/O) pad structures; and

fabricating an MPGA device based on said design, said design configured so that said fabricating of said MPGA device is separate from fabrication of an FPGA according to said design, said MPGA device comprising a circuit layout comprising a subset of said plurality of said sub-regions that are in said design, said circuit layout of said MPGA device comprising a substantially identical layout as in said first region of said design but excluding said register at said boundary of said first region, wherein said MPGA device further comprises a substantially identical layout of one or more of said layers of programmable interconnects as in said first region of said design;

wherein said first region in said design is identically mapped to said MPGA device.

22. The method of claim 21, wherein said design for said FPGA comprises a plurality of input/output (I/O) pads arranged around a perimeter of said core region, wherein said MPGA device interfaces with a subset of said plurality of I/O pads that are in said design.

23. The method of claim 21, wherein said design comprises power and ground pad structures that are arranged in positions that are common to all of said sub-regions.

24. The method of claim 21, wherein said MPGA device further comprises:

a first module layer comprising field programmable logic blocks; and

a second module layer adjacent to said first module layer and comprising routing circuitry coupled to said field programmable logic blocks of said MPGA device.

25. The method of claim 21, further comprising:

identifying a timing difference between an input/output (I/O) delay for said design and an I/O delay determined for said MPGA device; and

compensating for said timing difference in said MPGA device.

26. The method of claim 21, wherein said plurality of sub-regions comprises a first region and a second region positioned concentrically about the perimeter of said first region.

27. The method of claim 21, wherein sub-regions of said plurality of sub-regions share a first boundary and a second boundary.

28. The method of claim 21, wherein said MPGA device further comprises a customized metal circuit to mask program programmable logic blocks and programmable interconnects in said MPGA device.

29. The method of claim 28, wherein said customized metal circuit is selected from the group consisting of:

wire connection, wire disconnect, via connection, resistor element, shorted capacitor, capacitor, power bus connection, ground bus connection, transistor short, logic zero output connection, and logic one output connection.

30. The method of claim 21, wherein said MPGA device and said first region of said design further comprise a substantially identical layout of one or more pass-gate devices configured to couple a field programmable logic block to an interconnect wire, wherein in said MPGA device, said pass-gate device is operable for coupling said logic block to said interconnect wire, said pass-gate device is controlled by an output of a ROM bit, and said ROM bit comprises:

a metal connection to a power bus to couple said field programmable logic block to said interconnect wire; and

a metal connection to a ground bus to decouple said field programmable logic block from said interconnect wire.

31. The method of claim 21, wherein said MPGA device and said first region of said design further comprise a substantially identical layout of one or more pass-gate devices configured to couple a field programmable logic block to an interconnect wire, wherein in said MPGA device, said pass-gate device is decoupled from said interconnect wire when a RAM bit comprises a logic zero.