Method of self-synchronization of configurable elements of a programmable module
First Claim
1. A method for controlling data processing by an integrated circuit that includes a plurality of data processing elements that are arranged for at least one of arithmetically and logically processing data using a sequence of commands, the sequence including jumps, the method comprising:
- for each of a plurality of the processing elements that each include at least one corresponding register;
predefining at least one corresponding configuration command; and
storing each of the at least one corresponding configuration command in one of the at least one register corresponding to the processing element;
processing data in at least one first processing element;
obtaining at least one of a comparison, a sign, a carryover, and an error state during the processing of the data in the at least one first processing element;
in response to the at least one of the comparison, the sign, the carry-over, and the error state, generating for the at least one second processing element at least one first synchronization signal within a data stream during runtime;
processing data in at least one second processing element in a stream-like manner; and
in response to the at least one first synchronization signal, selecting at least one particular command from the stored configuration commands in order to control a jump in the sequence.
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Accused Products
Abstract
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.
644 Citations
122 Claims
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1. A method for controlling data processing by an integrated circuit that includes a plurality of data processing elements that are arranged for at least one of arithmetically and logically processing data using a sequence of commands, the sequence including jumps, the method comprising:
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for each of a plurality of the processing elements that each include at least one corresponding register; predefining at least one corresponding configuration command; and storing each of the at least one corresponding configuration command in one of the at least one register corresponding to the processing element; processing data in at least one first processing element; obtaining at least one of a comparison, a sign, a carryover, and an error state during the processing of the data in the at least one first processing element; in response to the at least one of the comparison, the sign, the carry-over, and the error state, generating for the at least one second processing element at least one first synchronization signal within a data stream during runtime; processing data in at least one second processing element in a stream-like manner; and in response to the at least one first synchronization signal, selecting at least one particular command from the stored configuration commands in order to control a jump in the sequence.
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2. A Field Programmable Gate Array integrated circuit, comprising:
- a multi-dimensionally arranged configurable element structure including configurable elements;
an interconnection system for interconnecting the configurable elements; and at least one of a unit and an interface for configuring the configurable elements; wherein; each of at least one of the configurable elements; is adapted for data processing; includes; at least one configuration register adapted for receiving and storing therein during runtime at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection; at least two data inputs and at least one data output connected to the interconnection system; at least one arithmetic-logic-unit; and
at least one status information input from the interconnection system; and
is adapted for being configured by the at least one of the unit and the interfacewith at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- a multi-dimensionally arranged configurable element structure including configurable elements;
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16. A Field Programmable Gate Array integrated circuit comprising:
- a multi-dimensionally arranged configurable element structure including a plurality of configurable elements;
an interconnection system for interconnecting the configurable elements; and
at least one of a unit and an interface for configuring and reconfiguring the configurable elements;wherein each of at least one of the configurable elements;
is adapted for data processing;
includes;
at least two data inputs and at least one data output connected to the interconnection system;at least one arithmetic-logic-unit;
a configuration interface input; and
at least one configuration register adapted for receiving, during runtime, from at least one other of the configurable elements, and via the configuration interface input and the interconnection system, and storing during runtime, at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection; andis adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
- a multi-dimensionally arranged configurable element structure including a plurality of configurable elements;
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29. A configurable element arrangement adapted for implementation in an integrated circuit, the integrated circuit comprising:
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a multi-dimensionally arranged configurable element structure including a plurality of configurable elements; an interconnection system for interconnecting the configurable elements; and
at least one of a unit and an interface for configuring the configurable elements;
wherein each of at least one of the configurable elements;comprises;
at least two data inputs and at least one data output connected to the interconnection system;at least one arithmetic-logic-unit;
a configuration interface input; and
at least one configuration register adapted for receiving, during runtime, via the configuration interface input and the interconnection system, and from a unit other than the at least one of the unit and the interface, and storing during runtime, at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;is adapted for being configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; and is adapted for data processing. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. A data processing integrated circuit, comprising:
- a multi-dimensionally arranged configurable element structure including a plurality of configurable elements;
at least one of the configurable elements;
comprises;
at least two data inputs and at least one data output connected to the interconnection system;at least one arithmetic-logic-unit;
a configuration interface input; and
at least one configuration register adapted for receiving, during runtime and via the configuration interface input and the interconnection system, and storing during runtime, at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;is adapted for being configured, by (a) the at least one of the unit and the interface and (b) at least one other of the configurable elements, and with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; and adapted for data processing. - View Dependent Claims (54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
- a multi-dimensionally arranged configurable element structure including a plurality of configurable elements;
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64. A data processing integrated circuit comprising:
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configurable elements arranged in a multi-dimensional pattern; an interconnection system for interconnecting the configurable elements; and at least one of a unit and an interface for configuring the configurable elements;
wherein each of at least some of the configurable elements;
comprises;
at least one arithmetic unit;
at least two operand registers;
at least one result register;
at least one input interface to the interconnection system for receiving status information generated by another of the configurable elements from the interconnection system;at least one configuration data input; and
at least one configuration register adapted for receiving, at runtime and via the at least one configuration data input, and storing during runtime, at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;is adapted for being configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; and is adapted to process the at least two operands arithmetically according to the at least one configuration code and received status information. - View Dependent Claims (65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80)
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81. A Field Programmable Gate Array integrated circuit comprising:
- configurable elements arranged in a multi-dimensional pattern;
an interconnection system for interconnecting the configurable elements; and
at least one of a unit and an interface for configuring the configurable elements;
wherein each of at least some of the configurable elements;
comprises;
at least one arithmetic unit;
at least two operand registers;
at least one result register;at least one input interface to the interconnection system for receiving status information generated by another of the configurable elements from the interconnection system; at least one configuration data input; and
at least one configuration register adapted for receiving, during runtime and via the at least one configuration data input, and storing during runtime at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection;is adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; and is adapted to process the at least two operands arithmetically according to the configuration data and received status information. - View Dependent Claims (82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94)
- configurable elements arranged in a multi-dimensional pattern;
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95. A Field Programmable Gate Array integrated circuit comprising:
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configurable elements arranged in a multi-dimensional pattern;
an interconnection system for interconnecting the configurable elements; and
at least one of a unit and an interface for configuring the configurable elements;
wherein each of at least some of the configurable elements;is adapted to receive at least one configuration code from said at least one of the unit and the interface; comprises;
at least one arithmetic unit;
at least two operand registers;
at least one result register;
at least one configuration data input for receiving at runtime, from at least one other of the configurable elements and via the interconnection system, at least one additional configuration code, each of the at least one additional configuration code representing only one of a single respective function and a single respective interconnection of the configurable element; andat least one configuration register adapted for storing therein at runtime the at least one additional configuration code; is adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one additional configuration code; and is adapted to process at least two operands of the at least two operand registers arithmetic-logically according to the at least one additional configuration code received from the configuration data input and the at least one configuration code provided by said at least one of the unit and the interface. - View Dependent Claims (96, 97, 98, 99, 100, 101, 102)
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103. A data processing integrated circuit comprising:
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configurable elements arranged in a multi-dimensional pattern; an interconnection system for interconnecting the configurable elements; and
at least one of a unit and an interface for configuring the configurable elements;
wherein each of at least some of the configurable elements;
is adapted to receive at least one configuration code from said at least one of the unit and the interface;comprises;
at least one arithmetic unit;
at least two operand registers;
at least one result register;
at least one configuration data input for receiving at runtime, from at least one other of the configurable elements and via the interconnection system, at least one additional configuration code, each of the at least one additional configuration code representing only one of a single respective function and a single respective interconnection of the configurable element; andat least one configuration register adapted for storing therein at runtime the at least one additional configuration code; is adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one additional configuration code; and is adapted to process at least two operands of the at least two operand registers arithmetic-logically according to the at least one additional configuration code received from the configuration data input and the at least one configuration code provided by said at least one of the unit and the interface. - View Dependent Claims (104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114)
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115. A runtime configurable integrated data processing circuit, comprising:
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a plurality of configurable elements arranged in a multi-dimensional structure; and
a configurable interconnection for connecting the plurality of configurable elements;
wherein;
each of at least some of the plurality of configurable elements;
includes;
at least two operand registers for receiving operand data from the configurable interconnection;at least one result register for transmitting result data to the configurable interconnection; at least one arithmetic unit;
at least one configuration input for configuring at least an operation performed by the at least one arithmetic unit;at least one multiplexer located between at least one of the operand registers and the arithmetic unit, the at least one of the operand registers being adapted for feeding at least a first one of inputs of the multiplexer; and at least one feedback from the at least one result register to at least one input of the at least one multiplexer adapted for feeding result data back to the at least one arithmetic unit; and is adapted for transmitting at runtime its result as at least one configuration code to the configuration input of at least one other of the at least some of the plurality of configurable elements via the interconnection; each of the at least one other of the at least some of the plurality of configurable elements; includes at least one configuration register adapted for storing therein during runtime the at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection; and is adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; and at least some of the configurable elements are adapted for processing data according to their configuration. - View Dependent Claims (116, 117, 121)
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118. A runtime configurable integrated data processing circuit, comprising:
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a plurality of configurable elements arranged in a multi-dimensional structure; and
a configurable interconnection for connecting the plurality of configurable elements;
wherein;
each of at least some of the plurality of configurable elements;
includes;
at least two operand registers;
at least one result register;at least one arithmetic-logic unit adapted to perform a computer operation producing a result; at least one configuration input for configuring at least the computer operation performed by the at least one arithmetic-logic unit; at least one multiplexer located between at least one of the operand registers and the arithmetic-logic unit, the at least one of the operand registers adapted for feeding at least a first one of inputs of the multiplexer; and at least one feedback from the at least one result register to at least one input of the at least one multiplexer adapted for feeding result data back to the at least one arithmetic-logic unit; and is adapted for transmitting its output as at least one configuration code to the configuration input of at least one other of the at least some of the plurality of configurable elements via the interconnection; each of the at least one other of the at least some of the plurality of configurable elements; includes at least one configuration register adapted for storing therein during runtime the at least one configuration code, each of the at least one configuration code representing only one of a single respective function and a single respective interconnection; and is adapted to be configured with at least one of the respective single function and the respective single interconnection represented by one or more of the at least one configuration code; and at least some of the configurable elements are adapted to process data according to their configuration. - View Dependent Claims (119, 120, 122)
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Specification