Compact FPGA-based digital motor controller

• US RE45,388 E1
• Filed: 07/16/2013
• Issued: 02/24/2015
• Est. Priority Date: 07/13/2009
• Status: Active Grant

• Current Assignee: Hamilton Sundstrand Space Systems International Inc (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Hamilton Sundstrand Space Systems International Inc (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Wichowski, Robert, Hansen, Harold J., Hawes, Kevin G.
• Primary Examiner(s): Leykin, Rita
• Application Number:
  US13/943,193
• Time in Patent Office: 588 Days
• Field of Search: 318/400.04, 318/599, 318/400.01, 318/700, 318/254.1, 318/721, 318/722, 318/723, 318/724, 318/687, 318/268, 318/437, 318/400.29, 318/400.14, 318/400.13, 318/400.16, 318/445, 318/453, 318/454, 318/456, 318/458, 318/461, 318/465, 318/466, 318/470, 318/489, 318/600, 388/800
• US Class Current: 318/400.13
• CPC Class Codes: H02P 6/17 and for generating speed information
• CPC Class Codes: H02P 6/34 Modelling or simulation for control purposes

Abstract

A compact field programmable gate array (FPGA)-based digital motor controller (102), a method, and a design structure are provided. The compact FPGA-based digital motor controller (102) includes a sensor interface (206) configured to receive sensor data from one or more sensors (104) and generate conditioned sensor data. The one or more sensors (104) provide position information for a DC brushless motor (108). The compact FPGA-based digital motor controller (102) also includes a commutation control (210) configured to create switching commands to control commutation for the DC brushless motor (108). The commutation control (210) generates commutation pulses from the conditioned sensor data of the sensor interface (206). The compact FPGA-based digital motor controller (102) also includes a time inverter (208) configured to receive the commutation pulses. The time inverter (208) converts the commutation pulses into a rotational speed of the DC brushless motor (108) to provide a linear feedback control parameter.

Claims

1. A compact field programmable gate array (FPGA)-based digital motor controller (102) comprising:

a sensor interface (206) implemented in hardware circuitry configured to receive sensor data from one or more sensors (104) and generate conditioned sensor data, the one or more sensors (104) to provide position information for a direct current (DC) brushless motor (108);

a commutation control (210) implemented in hardware circuitry configured to create switching commands to control commutation for the DC brushless motor (108), the commutation control (210) generating commutation pulses from the conditioned sensor data of the sensor interface (206); and

a time inverter (208) implemented in hardware circuitry configured to receive the commutation pulses from the commutation control (210) and convert the commutation pulses into a rotational speed of the DC brushless motor (108) to provide a linear feedback control parameter;

wherein accuracy of the time inverter (208) is scalable.

2. The compact FPGA-based digital motor controller (102) of claim 1 further comprising:

data registers (204) configured to store command and status information; and

a communication interface (202) in communication with the data registers (204) to provide communication with a system controller (122).

3. The compact FPGA-based digital motor controller (102) of claim 2 further comprising:

a linear digital compensation filter (212) configured to receive the rotational speed from the time inverter (208) and a speed command from the data registers (204), the linear digital compensation filter (212) outputting a compensation command to the commutation control (210) responsive to the rotational speed and the speed command.

4. The compact FPGA-based digital motor controller (102) of claim 3 wherein the time inverter (208) is implemented in a first compact FPGA (214) and the linear digital compensation filter (212) is implemented in a second compact FPGA (216).

5. The compact FPGA-based digital motor controller (102) of claim 1 wherein accuracy of the time inverter (208) is scalable.

6. The compact FPGA-based digital motor controller (102) of claim 1 wherein the commutation control (210) performs predictive control to filter self-generated noise.

7. The compact FPGA-based digital motor controller (102) of claim 1 wherein the compact FPGA-based digital motor controller (102) is implemented in antifuse technology.

8. A method for controlling a motor with a compact field programmable gate array (FPGA)-based digital motor controller (102) comprising:

receiving sensor data from one or more sensors (104) indicating position information for a direct current (DC) brushless motor (108);

generating conditioned sensor data at a sensor interface (206) implemented in hardware circuitry of the compact FPGA-based digital motor controller (102);

generating commutation pulses from the conditioned sensor data at a commutation control (210) implemented in hardware circuitry of the compact FPGA-based digital motor controller (102);

converting the commutation pulses into a rotational speed of the DC brushless motor (108) at a time inverter (208) implemented in hardware circuitry of the compact FPGA-based digital motor controller (102) to provide a linear feedback control parameter; and

creating switching commands at the commutation control (210) to control commutation for the DC brushless motor (108);

wherein accuracy of the time inverter (208) is scalable.

9. The method of claim 8 further comprising:

storing command and status information in data registers (204) of the compact FPGA-based digital motor controller (102); and

providing communication between the data registers (204) and a system controller (122) via a communication interface (202) of the compact FPGA-based digital motor controller (102).

10. The method of claim 9 further comprising:

receiving the rotational speed from the time inverter (208) and a speed command from the data registers (204) at a linear digital compensation filter (212) of the compact FPGA-based digital motor controller (102); and

outputting a compensation command to the commutation control (210) responsive to the rotational speed and the speed command.

11. The method of claim 10 wherein the time inverter (208) is implemented in a first compact FPGA (214) and the linear digital compensation filter (212) is implemented in a second compact FPGA (216).

12. The method of claim 8 wherein accuracy of the time inverter (208) is scalable.

13. The method of claim 8 wherein the commutation control (210) performs predictive control to filter self-generated noise.

14. The method of claim 8 wherein the compact FPGA-based digital motor controller (102) is implemented in antifuse technology.