External storage device and memory access control method thereof

• US RE45,857 E1
• Filed: 05/18/2012
• Issued: 01/19/2016
• Est. Priority Date: 07/14/1995
• Status: Expired due to Fees

• Current Assignee: Emergence Memory Solutions LLC
• Original Assignee: Solid State Storage Solutions, Inc.
• Inventors: Tamura, Takayuki, Shiota, Shigemasa, Katayama, Kunihiro, Naito, Masashi
• Primary Examiner(s): Wassum, Luke S
• Application Number:
  US13/475,679
• Time in Patent Office: 1,341 Days
• Field of Search: 714/718, 714/746, 714/719, 714/799, 714/819, 714/763, 714/E11.034, 714/6.1, 714/758, 365/185.33, 365/230.03, 365/200, 365/201
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence

Abstract

A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.

Claims

1. A storage device, comprising:

a non-volatile semiconductor memory which is electrically erasable and which has first and second portions coupled to first and second buses;

a system interface coupled with an external host system; and

a controller reading data from said non-volatile semiconductor memory and transmitting said data to said host system via said system interface in response to a read command received by said system interface from said host system; and

wherein said controller starts reading (N+n)th sector data from said first portion of said non-volatile semiconductor memory via said first bus, while said controller transmits Nth sector data that has been read from said second portion of said non-volatile semiconductor memory via said second bus, to said host system via said system interface, in response to said read command for successive sector data, where N and n are integers.

2. A storage device as claimed in claim 1,

wherein said controller, in response to said read command for successive sector data,

reads said Nth sector data from said non-volatile semiconductor memory into said controller,

carries out data processing for said Nth sector data,

transmits said Nth sector data after said data processing to said host system via said system interface,

starts reading said (N+n)th sector data from said non-volatile semiconductor memory for said data processing for said (N+n)th sector while said controller transmits said Nth sector data after said data processing to said host system via said system interface,

carries out said data processing for said (N+n)th sector data, and

transmits said (N+n)th sector data after said data processing to said host system via said system interface.

3. A storage device as claimed in claim 2,

wherein said data processing is error correction processing of successive sector data.

4. A storage device as claimed in claim 1, comprising an error correction circuit for said successive sector data, and

wherein said controller starts transmitting said (N+n)th sector data from said non-volatile semiconductor memory to said error correction circuit, while said controller transmits said Nth sector data that has been carried out error correction processing by said error correction circuit, to said host system via said system interface.

5. A storage device as claimed in claim 1,

wherein said “

n”

is one.

6. A storage device as claimed in claim 1,

wherein a size of said sector data is 512 bytes.

7. A storage device as claimed in claim 1,

wherein said non-volatile semiconductor memory is a flash memory.

8. A storage device as claimed in claim 1,

wherein said non-volatile semiconductor memory is electrically erasable in a size of a sector unit.

9. A storage device, comprising:

a non-volatile semiconductor memory which is electrically erasable and which has first and second portions coupled to first and second buses;

a system interface coupled with an external host system; and

a controller reading data from said non-volatile semiconductor memory and transmitting said data to said host system via said system interface in response to a read command received by said system interface from said host system; and

wherein said controller carries out data processing for sector data that has been read from said non-volatile semiconductor memory, and

wherein said controller starts reading (N+n)th sector data from said first portion of said non-volatile semiconductor memory via said first bus for said data processing for said (N+n)th sector data, while said controller transmits Nth sector data that has been carried out said data processing after having been previously read from said second portion of said non-volatile semiconductor memory via said second bus, to said host system via said system interface, in response to said read command for successive sector data, where N and n are integers.

10. A storage device, comprising:

a non-volatile semiconductor memory which is electrically erasable and where data is stored in sector data divisions, where said non-volatile semiconductor memory has a first memory section and a second memory section storing alternating sectors of the data, respectively, and where said first memory section and said second memory section are accessed by first and second buses, respectively;

a system interface coupled with an external host system; and

a controller reading successive sectors of said data from said non-volatile semiconductor memory, responsive to a read command for successive sectors from said host system, and transmitting said data to said host system via said system interface;

wherein in response to said read command for successive sector data, said controller reads an (N+n)th sector of sector data of said data, from said first memory section of said non-volatile semiconductor memory via said first bus, while said controller transmits an Nth sector of sector data of said data, that has been read from said second memory section of said non-volatile semiconductor memory via said second bus, to said host system via said system interface, where N and n are integers.

11. A storage device as claimed in claim 10,

wherein said controller, in response to said read command for successive sectors,

reads said Nth sector from said non-volatile semiconductor memory into said controller,

carries out data processing for said Nth sector,

transmits said Nth sector after said data processing, to said host system via said system interface,

reads said (N+n)th sector from said non-volatile semiconductor memory for said data processing for said (N+n)th sector, while said controller transmits said Nth sector after said data processing to said host system via said system interface,

carries out said data processing for said (N+n)th sector, and

transmits said (N+n)th sector after said data processing, to said host system via said system interface.

12. A storage device as claimed in claim 11,

wherein said data processing is error correction processing of successive sectors.

13. A storage device as claimed in claim 10, comprising an error correction circuit for said successive sectors, and

wherein said controller starts transmitting said (N+n)th sector from said non-volatile semiconductor memory to said error correction circuit, while said controller transmits said Nth sector data having completed error correction processing by said error correction circuit, to said host system via said system interface.

14. A storage device as claimed in claim 10,

wherein said “

n”

is one.

15. A storage device as claimed in claim 10,

wherein a size of said sectors is 512 bytes.

16. A storage device as claimed in claim 10,

wherein said non-volatile semiconductor memory is a flash memory.

17. A storage device as claimed in claim 10,

wherein said non-volatile semiconductor memory is electrically erasable in a size of a sector data division.

18. A storage device, comprising:

a non-volatile semiconductor memory which is electrically erasable and which has first and second portions coupled to first and second data portions of a combination bus acting as first and second buses, respectively;

a system interface adapted to couple data and commands between the system interface and an external host system; and

a controller that reads data from the non-volatile semiconductor memory and transmits the data to the system interface in response to a read command received by the system interface;

wherein the controller starts reading second sector data from the non-volatile semiconductor memory via the second data portion of the combination bus as the second bus, while the controller transmits first sector data that has been read from the non-volatile semiconductor memory via the first data portion of the combination bus as the first bus to the system interface, in response to the read command.

19. A storage device as claimed in claim 18, wherein the controller, in response to the read command for successive sector data,

reads Nth sector data from the non-volatile semiconductor memory into the controller,

carries out data processing for the Nth sector data,

transmits the Nth sector data after the data processing to the system interface,

starts reading (N+n)th sector data from the non-volatile semiconductor memory for the data processing for the (N+n)th sector while the controller transmits the Nth sector data after the data processing to the system interface,

carries out the data processing for the (N+n)th sector data, and

transmits the (N+n)th sector data after the data processing to the system interface.

20. A storage device as claimed in claim 19,

wherein the data processing comprises error correction processing for the successive sector data.

21. A storage device as claimed in claim 19 comprising an error correction circuit for the successive sector data, and

wherein the controller starts transmitting said (N+n)th sector data from the non-volatile semiconductor memory to the error correction circuit, while the controller transmits error-corrected Nth sector data to the system interface.

22. A storage device as claimed in claim 19,

wherein “

n”

is one.

23. A storage device as claimed in claim 18,

wherein a size of the sector data is 512 bytes.

24. A storage device as claimed in claim 18,

wherein the non-volatile semiconductor memory comprises flash memory.

25. A storage device as claimed in claim 18,

wherein the non-volatile semiconductor memory is electrically erasable in a size of a sector unit.

26. A storage device as claimed in claim 18, wherein the first and second data portions are more particularly, upper and lower data portions, respectively, of the combination bus.

27. A storage device, comprising:

a non-volatile memory which is erasable and which has first and second portions coupled to first and second buses;

a system interface coupled with an external host system; and

a controller reading data from said non-volatile memory and transmitting said data to said host system via said system interface in response to a read command received by said system interface from said host system; and

wherein said controller starts reading (N+n)th addressable-subdivision data from said first portion of said non-volatile memory via said first bus, while said controller transmits Nth addressable-subdivision data that has been read from said second portion of said non-volatile memory via said second bus, to said host system via said system interface, in response to said read command for successive addressable-subdivision data, where N and n are integers.