Three dimensional hexagonal matrix memory array

• US RE46,435 E1
• Filed: 05/30/2014
• Issued: 06/13/2017
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Petti, Christopher J., Scheuerlein, Roy E.
• Primary Examiner(s): Nguyen, Tuan H
• Application Number:
  US14/291,415
• Time in Patent Office: 1,110 Days
• Field of Search: 365 51, 365 63, 365 72, 365103, 257316, 257686
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G03F 7/2022 Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/112 Read-only memory structures [ROM] and multistep manufacturing processes therefor
• CPC Class Codes: H01L 27/224 comprising two-terminal components, e.g. diodes, MIM elements
• CPC Class Codes: H01L 27/2409 comprising two-terminal selection components, e.g. diodes
• CPC Class Codes: H01L 27/2481 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout
• CPC Class Codes: H01L 45/04 Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
• CPC Class Codes: H01L 45/06 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H01L 45/085 the species being metal cations, e.g. programmable metallization cells

Abstract

A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

Claims

1. A nonvolatile memory device, comprising:

a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern,

wherein the nonvolatile memory cells are arranged in a plurality of subarrays which are substantially parallelogram shaped and have a non-square corner,

wherein each subarray among the plurality of subarrays includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern;

wherein each of the plurality of subarrays has parallel sides that extend along a first direction and a non-parallel side that adjoins a respective driver circuit block for driving the subarray;

wherein the driver circuit blocks for the plurality of subarrays have a staggered layout such that a layout of each driver circuit block is shifted along the first direction from a horizontal line that is perpendicular to the first direction and passes through the non-square corner by a respective lateral offset distance; and

the lateral offset distances differ among one another among an entire set of driver circuit blocks that drive the plurality of subarrays.

2. The nonvolatile memory device of claim 1, wherein:

the plurality of nonvolatile memory cells comprises a plurality of pillar shaped current steering elements; and

the substantially hexagonal pattern comprises a repeating pattern of seven nonvolatile memory cells having a central nonvolatile memory cell surrounded by six other nonvolatile memory cells arranged in a hexagonal layout around the central nonvolatile memory cell.

3. The nonvolatile memory device of claim 1, wherein the device comprises:

a first nonvolatile memory cell,

a second nonvolatile memory cell, and

a third nonvolatile memory cell;

wherein the first nonvolatile memory cell, the second nonvolatile memory cell, and the third nonvolatile memory cell are equidistant from each other and are located in a same plane.

4. The nonvolatile memory device of claim 3, wherein the first nonvolatile memory cell, the second nonvolatile memory cell, and the third nonvolatile memory cell have a cell half pitch of less than about 32 nm.

5. The nonvolatile memory device of claim 1, wherein the device comprises a monolithic, three dimensional array of nonvolatile memory cells.

6. The nonvolatile memory device of claim 1, wherein each nonvolatile memory cell comprises a one time programmable or a rewritable cell selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, graphene switchable resistance material, phase change material memory, conductive bridge element, or switchable polymer memory.

7. The nonvolatile memory device of claim 5, wherein:

the monolithic, three dimensional array of nonvolatile memory cells is located over a silicon substrate;

at least one memory cell in a first device level of the array is located over another memory cell in a second device level over the silicon substrate; and

an integrated circuit comprising a driver circuit for the array of nonvolatile memory cells is located in the silicon substrate or on a surface of the silicon substrate.

8. The nonvolatile memory device of claim 1, further comprising

a plurality of word lines connected to the plurality of nonvolatile memory cells;

and

a plurality of bit lines connected to the plurality of nonvolatile memory cells.

9. The nonvolatile memory device of claim 8, wherein the first direction is a direction along which bit lines of the plurality of nonvolatile memory cells extend.

10. The nonvolatile memory device of claim 8, wherein the first direction is a direction along which word lines of the plurality of nonvolatile memory cells extend.

11. The nonvolatile memory device of claim 8, wherein the plurality of word lines cross the plurality of bit lines at an angle of about 60 degrees.

13. The nonvolatile memory device of claim 8, wherein:

the plurality of nonvolatile memory cells comprises a plurality of pillar shaped current steering elements; and

the substantially hexagonal pattern comprises a repeating pattern of seven nonvolatile memory cells having a central nonvolatile memory cell surrounded by six other nonvolatile memory cells arranged in a hexagonal layout around the central nonvolatile memory cell.

14. The nonvolatile memory device of claim 8, wherein the device comprises:

a first nonvolatile memory cell,

a second nonvolatile memory cell, and

a third nonvolatile memory cell;

wherein the first nonvolatile memory cell, the second nonvolatile memory cell, and the third nonvolatile memory cell are equidistant from each other and are located in a same plane.

15. The nonvolatile memory device of claim 14, wherein the first nonvolatile memory cell, the second nonvolatile memory cell, and the third nonvolatile memory cell have a cell half pitch of less than about 32 nm.

12. A nonvolatile memory device, comprising:

a monolithic, three dimensional array of nonvolatile memory cells located over a silicon substrate and comprising a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern; and

an integrated circuit comprising a driver circuit for the array of nonvolatile memory cells located in the silicon substrate or on a surface of the silicon substrate, and

wherein the nonvolatile memory cells are arranged in a plurality of subarrays which are substantially parallelogram shaped and have a non-square corner;

wherein each subarray among the plurality of subarrays includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern;

wherein each of the plurality of subarrays has parallel sides that extend along a first direction and a non-parallel side that adjoins a respective driver circuit block for driving the subarray;

wherein the driver circuit blocks for the plurality of subarrays have a staggered layout such that a layout of each driver circuit block is shifted along the first direction from a horizontal line that is perpendicular to the first direction and passes through the non-square corner by a respective lateral offset distance; and

the lateral offset distances differ among one another among an entire set of driver circuit blocks that drive the plurality of subarrays.

16. The nonvolatile memory device of claim 12, wherein each nonvolatile memory cell comprises a one time programmable or a rewritable cell selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, graphene switchable resistance material, phase change material memory, conductive bridge element, or switchable polymer memory.

17. The nonvolatile memory device of claim 12, further comprising:

a plurality of word lines connected to the plurality of nonvolatile memory cells; and

a plurality of bit lines connected to the plurality of nonvolatile memory cells.

18. The nonvolatile memory device of claim 17, wherein the first direction is a direction along which bit lines of the plurality of nonvolatile memory cells extend.

19. The nonvolatile memory device of claim 17, wherein the first direction is a direction along which word lines of the plurality of nonvolatile memory cells extend.

20. The nonvolatile memory device of claim 12, further comprising:

a plurality of word lines connected to the plurality of nonvolatile memory cells; and

a plurality of bit lines connected to the plurality of nonvolatile memory cells;

wherein the plurality of word lines cross the plurality of bit lines at an angle of about 60 degrees.