Data security method and device for computer modules
DCFirst Claim
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1. A security protection method for a computer module, said method comprising:
- inserting the computer module into a console;
initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module;
determining of a predetermined security status based upon a relationship of said console identification and said computer module identification;
selecting said predetermined security status; and
operating said computer module based upon said security status.
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Abstract
A security method for an attached computer module in a computer system. The security method reads a security identification number in an attached computer module and compares it to a security identification number in a console, which houses the attached computer module. Based upon a relationship between these numbers, a security status is selected. The security status determines the security level of operating the computer system.
283 Citations
63 Claims
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1. A security protection method for a computer module, said method comprising:
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inserting the computer module into a console; initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module; determining of a predetermined security status based upon a relationship of said console identification and said computer module identification; selecting said predetermined security status; and operating said computer module based upon said security status. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system for secured information transactions, the system comprising:
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a console comprising a peripheral controller housed in the console; a user identification input device coupled to the peripheral controller, the user identification input device being provided for user identification data; and an attached computer module coupled to the console, the attached computer module comprising a security memory device stored with the user identification data. - View Dependent Claims (9, 10)
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11. A method for operating a module computer into one of a plurality of network systems, the method comprising:
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providing a computer module, the module comprising a connection program; inserting the computer module into a computer console, the computer console having access to a network; receiving connection information from the computer console; configuring the connection program to adapt to the connection information; and establish a connection between the computer module and a server coupled to the network. - View Dependent Claims (12, 13)
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14. A computer system, comprising:
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a central processing unit (CPU); a low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions; and a mass storage device directly coupled to the CPU; wherein the CPU is configured to output a serial bit stream of Universal Serial Bus (USB) protocol information that is conveyed over the LVDS channel. - View Dependent Claims (15, 16, 17, 18)
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19. A computer system, comprising:
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a central processing unit (CPU); a mass storage device directly coupled to the CPU; and a low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions; wherein the LVDS channel is configured to output a serial bit stream of address bits, data bits, and byte enable information bits of a Peripheral Component Interface (PCI) bus transaction. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A computer system, comprising:
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an integrated central processing unit and graphics subsystem in a single chip directly connected to a Low Voltage Differential Signal (LVDS) channel to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and a mass storage device directly coupled to the integrated central processing unit and graphics subsystem, comprising flash memory; wherein the integrated central processing unit and graphics subsystem directly outputs a differential signal channel to convey digital video display signals. - View Dependent Claims (27, 28)
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29. A computer system, comprising:
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a printed circuit board coupled to a connector; a central processing unit (CPU); a first low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two sets of unidirectional, serial bit channels to convey an encoded serial bit stream of address bits, data bits, and byte enable information bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions; a mass storage device coupled to the CPU; and a second LVDS channel coupled to the connector, comprising two sets of unidirectional, serial bit channels to convey serial bit data in opposite directions. - View Dependent Claims (30, 31)
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32. A computer system, comprising:
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an integrated central processing unit and graphics subsystem in a single chip directly outputting digital video display signals to a differential signal channel; and a Low Voltage Differential Signal (LVDS) channel to convey Universal Serial Bus (USB) protocol signals, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; wherein the differential signal channel conveys Transition Minimized Differential Signaling (TMDS) signals. - View Dependent Claims (33, 34)
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35. A computer system, comprising:
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a printed circuit board coupled to a connector; a central processing unit; a mass storage unit coupled to the central processing unit; a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect (PCI) bus, wherein the peripheral bridge directly conveys an encoded serial bit stream of address bits, data bits, and byte enable information bits of a PCI bus transaction over the first LVDS channel; and a second LVDS channel coupled to the connector, comprising two sets of unidirectional, serial bit channels to convey serial bit data in opposite directions. - View Dependent Claims (36, 37, 38, 39, 40, 41)
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42. A computer, comprising:
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a central processing unit directly coupled to a first Low Voltage Differential Signal (LVDS) channel comprising at least two sets of unidirectional, serial bit channels to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial bit streams in opposite directions; a graphics subsystem directly coupled to a differential signal channel to convey digital video display signals; a connector coupled to the central processing unit through a second Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, differential signal pairs to convey serial bit data in opposite directions. - View Dependent Claims (43, 44, 45, 46, 47)
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48. A computer system comprising:
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a central processing unit (CPU) comprising an interface controller; a first low voltage differential signal (LVDS) channel directly extending from the interface controller, the first LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and a second LVDS channel coupled to a connector, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions; wherein the first LVDS channel conveys encoded serial bit streams of address bits, data bits, and byte enable information bits of Peripheral Component Interconnect (“
PCI”
) bus transactions. - View Dependent Claims (49, 50)
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51. A computer system comprising:
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a central processing unit (CPU); a peripheral bridge directly coupled to the CPU without any intervening Peripheral Component Interconnect (PCI) bus; a first low voltage differential signal (LVDS) channel directly coupled to the peripheral bridge, comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channels comprises four or more differential signal pairs; and a second LVDS channel extending directly from the CPU, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions; wherein the first LVDS channel conveys encoded serial bit streams of address bits, data bits, and byte enable information bits of PCI bus transactions. - View Dependent Claims (52, 53)
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54. A computer system comprising:
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a central processing unit (CPU) comprising an interface controller; a first low voltage differential signal (LVDS) channel directly extending from the interface controller, the first LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and a second LVDS channel coupled to a connector, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions; and wherein the first LVDS channel conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“
PCI”
) bus transaction. - View Dependent Claims (55, 56)
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57. A computer system comprising:
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a central processing unit (CPU); a peripheral bridge directly coupled to the CPU without any intervening Peripheral Component Interconnect (PCI) bus; a first low voltage differential signal (LVDS) channel directly coupled to the peripheral bridge, comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and a second LVDS channel extending directly from the CPU, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions; wherein the first LVDS channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction. - View Dependent Claims (58, 59)
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60. A computer comprising:
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a connector for external peripheral data communication; a central processing unit (CPU); a first Low Voltage Differential Signal (LVDS) channel directly connected to the CPU comprising two unidirectional, serial bit channels that transmit data in opposite directions; and a second LVDS channel to convey Universal Serial Bus (USB) protocol traffic through the connector, the second LVDS channel including two unidirectional, serial bit channels that transmit data in opposite direction; and wherein the connector further conveys digital video data through a third differential signal channel. - View Dependent Claims (61)
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62. A computer comprising:
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a connector for external peripheral data communication; an integrated central processing unit and graphics subsystem in a single chip; and a first Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, serial bit channels that transmit data in opposite directions; wherein the integrated graphics subsystem directly outputs digital video display data to a unidirectional differential signal channel; wherein the first LVDS channel conveys Universal Serial Bus (USB) protocol traffic through the connector and wherein the digital video display data couples to the connector. - View Dependent Claims (63)
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Specification