Forming semiconductor cells with regions of varying conductivity
First Claim
1. A semiconductor memory cell comprising:
- a substrate having a top surface, said substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type, said first region being formed in said substrate and exposed at said top surface;
a second region having said second conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface;
a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;
a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type;
a gate positioned between said first and second regions and above said top surface; and
a nonvolatile memory configured to store data upon transfer from said body region;
wherein a data state of said body region is maintained by applying a voltage to said substrate.
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Accused Products
Abstract
A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region and having the first conductivity type; and a gate positioned between the first and second regions and above the top surface; wherein a state of the body region is maintained by applying a voltage to the substrate and a nonvolatile memory configured to store data upon transfer from the body region.
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Citations
31 Claims
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1. A semiconductor memory cell comprising:
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a substrate having a top surface, said substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type, said first region being formed in said substrate and exposed at said top surface; a second region having said second conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface; a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type; a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type; a gate positioned between said first and second regions and above said top surface; and a nonvolatile memory configured to store data upon transfer from said body region; wherein a data state of said body region is maintained by applying a voltage to said substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A semiconductor memory cell comprising:
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an arrangement of layers having alternating conductivity types selected from p-type conductivity type and n-type conductivity type configured to function as a silicon controlled rectifier device to store data in volatile memory; and a nonvolatile memory configured to store data upon transfer from volatile memory. - View Dependent Claims (24, 25, 26, 27, 28)
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29. A method of operating a memory cell having a floating body for storing, reading and writing data as volatile memory, and a nonvolatile memory for storing data, the method comprising:
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reading and storing data to the floating body while power is applied to the memory cell; biasing a substrate terminal connected to a substrate of said memory cell to operate said memory cell as a silicon rectifier device in a conducting operation when said floating body has a first data state, but wherein a blocking operation results when said floating body has a second data state; and transferring the data stored in the floating body to the nonvolatile memory when power to the cell is interrupted.
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30. A method of operating a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a resistance change element for storing data as non-volatile memory, the method comprising:
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reading and storing data to the floating bodies as volatile memory while power is applied to the device; biasing a substrate terminal connected to a substrate of said memory cell to operate said memory cell as a silicon rectifier device in a conducting operation when said floating body has a first data state, but wherein a blocking operation results when said floating body has a second data state; transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the resistance change elements corresponding to the floating bodies, when power to the device is interrupted; and storing the data in the resistance change elements as non-volatile memory. - View Dependent Claims (31)
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Specification