Power semiconductor having a lightly doped drift and buffer layer

• US RE47,710 E1
• Filed: 02/20/2015
• Issued: 11/05/2019
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Zundel, Markus, Hirler, Franz, Willmeroth, Armin
• Primary Examiner(s): Andujar, Leonardo
• Application Number:
  US14/627,735
• Time in Patent Office: 1,719 Days
• CPC Class Codes: N/A

Abstract

A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.

Claims

1. A power MOS transistor of the planar type, comprising:

a semiconductor body having a first and a second surface,

body regions of a first conductivity type and a first dopant concentration formed in the first surface;

a highly doped source region of a second conductivity type having a first dopant concentration, provided at the first surface;

a contact arrangement provided at the first surface, the contact arrangement comprising a gate electrode over an insulating layer on the first surface and source electrode, directly over the first surface and in contact with the source region;

at least two deep, lightly doped well regions of the first conductivity type having a second dopant concentration, and having a minimum lateral distance therebetween;

a highly doped drain contact layer of the second conductivity type and a second dopant concentration provided in or on the second surface of the semiconductor body; and

an electrode provided on the free surface of the drain contact layer;

wherein underneath and between the deep well regions of the first conductivity type a lightly doped drift and buffer layer of the second conductivity type and a third dopant concentration is provided, wherein the drift and buffer layer has a minimum vertical extension between the drain contact layer and the bottom of the deepest well region which is at least equal to the minimum lateral distance between the deep well regions

wherein the vertical extension of the drift and buffer layer amounts to at least twice the minimum lateral distance between the deep well regions; and

wherein the vertical extension of the drift and buffer layer between the drain contact layer and the bottom of the deepest well region is determined such that a total amount of its dopants per unit area is larger than a breakdown charge amount.

2. The power transistor of claim 1, wherein the second dopant concentration in the drift and buffer layer increases towards the drain contact layer.

3. The power transistor of claim 1, of the superjunction type, wherein the deep, lightly doped well regions are constituted by a basically vertical stack of separated, bubble-shaped well regions.

4. The power transistor of claim 1, wherein the semiconductor body and the drift and buffer layer comprise a semiconductor substrate and the drain contact layer comprises an ion implantation layer within the semiconductor substrate.

5. The power transistor of claim 1, wherein the second dopant concentration is constant through the drift and buffer layer.

6. The power transistor of claim 1, wherein an interface between the drift and buffer layer and the drain contact layer comprises valleys under the deep well regions.

7. A super junction power transistor of a trench type, comprising:

a semiconductor body having a first surface and a second surface;

a body region of a first conductivity type and a first dopant concentration formed in the first surface;

a source region of a second conductivity type provided at the first surface;

a contact arrangement which comprises a source electrode over a first insulating layer on the first surface and in contact with the source region and a gate electrode provided within a trench extending vertically into the first surface of the semiconductor body and being separated from walls of the trench by a second insulating layer;

at least two deep well regions of the first conductivity type having a second dopant concentration, the deep well regions having a minimum lateral distance therebetween and having a shallow well region disposed therebetween, and wherein the deep well regions are constituted by a vertical stack of bubble-shaped well regions;

a drain contact layer of the second conductivity type provided at the second surface;

an electrode provided on a surface of the drain contact layer; and

a drift and buffer layer of the second conductivity type and including a third dopant concentration, wherein the drift and buffer layer is provided underneath the deep well regions of the first conductivity type,

wherein the drift and buffer layer has a minimum vertical extension between the drain contact layer and a bottom of a deepest well region of the deep well regions and which is at least equal to the minimum lateral distance between the deep well regions.

8. The super junction power transistor of claim 7, wherein the minimum vertical extension of the drift and buffer layer amounts to at least twice the minimum lateral distance between the deep well regions.

9. The super junction power transistor of claim 7, wherein the minimum vertical extension of the drift and buffer layer between the drain contact layer and the bottom of the deepest well region is determined such that a total amount of its dopants per unit area is larger than a breakdown charge amount.

10. The super junction power transistor of claim 7, wherein the third dopant concentration in the drift and buffer layer increases towards the drain contact layer.

11. The super junction power transistor of claim 7, wherein the third dopant concentration is constant through the drift and buffer layer.

12. The super junction power transistor of claim 7, wherein the semiconductor body and the drift and buffer layer comprise a semiconductor substrate and the drain contact layer comprises an ion implantation layer within the semiconductor substrate.

13. The super junction power transistor of claim 7, wherein the power semiconductor is capable of blocking at least one reverse voltage within a range of 40 V to 1200V.

14. The super junction power transistor of claim 7, wherein the minimum vertical extension of the drift and buffer layer is determined such that the total amount of the dopants per unit area is within a range of a factor of 1.5-2.5 of a charge at breakdown voltage.

15. The super junction power transistor of claim 7, further comprising a drift layer of the second conductivity type, located between the deep well regions and having a fourth dopant concentration,

wherein the third dopant concentration is located underneath the deep well regions and is within a range of a factor of 0.01 to 3 of the fourth dopant concentration.

16. A super junction power transistor of a trench type, comprising:

a semiconductor body having a first surface and a second surface;

a body region of a first conductivity type and a first dopant concentration formed in the first surface;

a source region of a second conductivity type provided at the first surface;

a contact arrangement with a trench which extends into the first surface;

at least two well regions of the first conductivity type having a second dopant concentration, and having a minimum lateral distance therebetween;

a drain contact layer of the second conductivity type provided at the second surface;

an electrode provided on a surface of the drain contact layer; and

a drift and buffer layer of the second conductivity type and including a third dopant concentration is provided underneath the well regions of the first conductivity type,

wherein the drift and buffer layer has a minimum vertical extension between the drain contact layer and a bottom of a deepest well region of the well regions and which is at least equal to the minimum lateral distance between the well regions.

17. The super junction power transistor of claim 16, wherein the contact arrangement comprises a gate electrode provided within the trench extending vertically into the first surface of the semiconductor body and being separated from walls of the trench by a second insulating layer.

18. The super junction power transistor of claim 16, wherein the well regions are constituted by a vertical stack of bubble-shaped well regions.

19. The super junction power transistor of claim 16, wherein the minimum vertical extension of the drift and buffer layer amounts to at least twice the minimum lateral distance between the well regions.

20. The super junction power transistor of claim 16, wherein the minimum vertical extension of the drift and buffer layer between the drain contact layer and the bottom of the deepest well region is determined such that a total amount of its dopants per unit area is larger than a breakdown charge amount.

21. The super junction power transistor of claim 16, wherein the third dopant concentration in the drift and buffer layer increases towards the drain contact layer.

22. The super junction power transistor of claim 16, wherein the third dopant concentration is constant through the drift and buffer layer.

23. The super junction power transistor of claim 16, wherein the semiconductor body and the drift and buffer layer comprise a semiconductor substrate and the drain contact layer comprises an ion implantation layer within the semiconductor substrate.

24. The super junction power transistor of claim 16, wherein the power semiconductor is capable of blocking at least one reverse voltage within a range of 40 V to 1200V.

25. The super junction power transistor of claim 16, wherein the minimum vertical extension of the drift and buffer layer is determined such that the total amount of the dopants per unit area is within a range of a factor of 1.5-2.5 of a charge at breakdown voltage.

26. The super junction power transistor of claim 16, further comprising a drift layer of the second conductivity type, located between the well regions, and having a fourth dopant concentration,

wherein the third dopant concentration is located underneath the well regions and is within a range of a factor of 0.01 to 3 of the fourth dopant concentration.

27. A power semiconductor, comprising:

a semiconductor body having a first surface and a second surface;

a body region of a first conductivity type and a first dopant concentration formed in the first surface;

a source region of a second conductivity type provided at the first surface;

a contact arrangement provided at the first surface;

at least two well regions of the first conductivity type having a second dopant concentration, and having a minimum lateral distance therebetween;

a drain contact layer of the second conductivity type provided in or on the second surface of the semiconductor body;

an electrode provided on a surface of the drain contact layer;

a drift layer of the second conductivity type, wherein the drift layer is provided underneath and between the well regions of the first conductivity type; and

a buffer layer of the second conductivity type provided underneath the drift layer,

wherein a portion of the drift layer that is provided underneath the well regions combined with the buffer layer have a minimum vertical extension between the drain contact layer and a bottom of a deepest well region of the well regions and which is at least equal to the minimum lateral distance between the well regions,

wherein the power semiconductor is a super junction power transistor of a trench type.

28. The power semiconductor of claim 27, wherein the contact arrangement comprises a gate electrode provided within a trench extending vertically into the first surface of the semiconductor body and being separated from walls of the trench by a second insulating.

29. The power semiconductor of claim 27, wherein the deep, lightly doped well regions are constituted by a vertical stack of bubble-shaped well regions.

30. The power semiconductor of claim 27, wherein the minimum vertical extension amounts to at least twice the minimum lateral distance between the well regions.

31. The power semiconductor of claim 27, wherein the minimum vertical extension is determined such that a total amount of its dopants per unit area is larger than a breakdown charge amount.

32. The power semiconductor of claim 27, wherein the semiconductor body, the drift layer and the buffer layer comprise a semiconductor substrate and the drain contact layer comprises an ion implantation layer within the semiconductor substrate.

33. The power semiconductor of claim 27, wherein the power semiconductor is capable of blocking at least one reverse voltage within a range of 40 V to 1200V.

34. The power semiconductor of claim 27, wherein the minimum vertical extension is determined such that the total amount of the dopants per unit area is within a range of a factor of 1.5-2.5 of a charge at breakdown voltage.

35. The power semiconductor of claim 27, wherein the portion of the drift layer provided underneath the well regions and the buffer layer together include a third dopant concentration, and

the drift layer, located between the well regions, has a fourth dopant concentration, wherein the third dopant concentration is within a range of a factor of 0.01 to 3 of the fourth dopant concentration.

36. The power semiconductor of claim 35, wherein the third dopant concentration increases towards the drain contact layer.

37. The power semiconductor of claim 35, wherein the third dopant concentration is constant through the portion of the drift layer that is provided underneath the well regions and the buffer layer.