Apparatus and method for the characterization of analog-to-digital converters

• US RE47,805 E1
• Filed: 12/01/2016
• Issued: 01/07/2020
• Est. Priority Date: 05/07/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mattes, Heinz
• Primary Examiner(s): Leung, Christina Y.
• Application Number:
  US15/366,643
• Time in Patent Office: 1,132 Days
• CPC Class Codes: N/A

Abstract

A method and apparatus for characterizing an A/D converter are provided. The A/D converter is configured to convert an input signal into a digital output signal. The method and apparatus may provide: applying an input signal to the A/D converter that in a first phase at least includes a gradient of a rising exponential function with Euler'"'"'s number as the base, and in a further phase has a profile of a falling exponential function with Euler'"'"'s number as the base, integrating a digital output signal associated with the A/D converter during the first phase to provide a first sum, integrating the digital output signal associated with the A/D converter during the further phase to provide a second sum, and calculating from the first sum and the second sum at least a gain error of the A/D converter and/or a zero point error of the A/D converter.

Claims

1. A method of characterizing an analog-to-digital converter, the analog-to-digital converter configured to convert an input signal to a digital output signal, the method comprising:

applying the input signal to the analog-to-digital converter that in a first phase at least includes a profile of a rising exponential function with Euler'"'"'s number as the base, and in a further phase has a profile of a falling exponential function with Euler'"'"'s number as the base;

integrating the digital output signal during the first phase to provide a first sum;

integrating the digital output signal during the further phase to provide a second sum; and

calculating from the first sum and the second sum at least one of a gain error of the analog-to-digital converter and/or and a zero-point error of the analog-to-digital converter.

2. The method according to claim 1, wherein the rising and falling exponential functions make use of a common time constant.

3. The method according to claim 1, further comprising scanning the input signal using a constant sampling frequency.

4. The method according to claim 1, wherein the rising exponential function is given by

5. The method according to claim 1, wherein the falling exponential function is given by u(t)=u₀*e⁽⁻

t/τ

), wherein t is time, τ

is a time constant, u₀ is a constant, wherein u₀ is smaller than or equal to a size of an input range of the analog-to-digital converter.

6. The method according to claim 1, wherein the first phase has a time duration of T₁ and the second phase has a time duration of T₂, T₁=T₂=ln(2)*τ

, wherein τ

is a time constant of the exponential functions.

7. The method according to claim 3, wherein the constant sampling frequency is greater than 2^B*1/(T₁), where T₁ is a time duration of the first phase and B is a resolution of the analog-to-digital converter.

8. The method according to claim 1, wherein calculating includes determining a difference value from the first sum and the second sum.

9. An electrical circuit for characterizing an analog-to-digital converter, the analog-to-digital converter configured to convert an input signal to a digital output signal, the electrical circuit comprising:

a generator to provide the input signal, the input signal in a first phase at least includes a profile of a rising exponential function with Euler'"'"'s number as the base, and in a further phase has a profile of a falling exponential function with Euler'"'"'s number as the base

an integrator to integrate the digital output signal during the first phase 2 to provide a first sum and to integrate the digital output signal during the further phase to provide a second sum;

a calculation unit to calculate from the first sum and the second sum at least one of a gain error of the analog-to-digital converter and/or and a zero-point error of the analog-to-digital converter.

10. The electrical circuit according to claim 9, wherein the rising and falling exponential functions make use of a common time constant.

11. The electrical circuit according to claim 9, scanning wherein the analog-to-digital converter is configured to scan the input signal has at a constant sampling frequency.

12. The electrical circuit according to claim 9, wherein the rising exponential function is given by

13. The electrical circuit according to claim 9, wherein the falling exponential function is given by u(t)=u₀*e⁽⁻

t/τ

), wherein t is time, τ

is a time constant, u₀ is a constant, wherein u₀ is smaller than or equal to a size of an input range of the analog-to-digital converter.

14. The electrical circuit according to claim 9, wherein the first phase has a time duration of T₁ and the second phase has a time duration of T₂, T₁=T₂=ln(2)*τ

, wherein τ

is a time constant of the exponential functions.

15. The electrical circuit according to claim 11, wherein the constant sampling frequency is greater than 2^B*1/(T₁), where T₁ is a time duration of the first phase and B is a resolution of the analog-to-digital converter.

16. The electrical circuit according to claim 9, wherein the electrical circuit in the analog-to-digital converter are monolithically integrated.

17. The electrical circuit according to claim 9, wherein the calculation unit comprises a summation unit for calculating a sum from the first sum and the second sum and a difference unit for determining a difference between the first sum and the second sum.