Active CMOS recovery units for wireless power transmission

• US 10,003,278 B2
• Filed: 11/24/2014
• Issued: 06/19/2018
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Hajimiri, Seyed Ali, Abiri, Behrooz, Bohn, Florian
• Primary Examiner(s): Chang, Joseph
• Application Number:
  US14/552,249
• Publication Number:
  US 20150145350A1
• Time in Patent Office: 1,303 Days
• Field of Search: 307149
• CPC Class Codes: H02J 5/00 Circuit arrangements for transfer of electric power between ac networks and dc networks H02J3/36 takes precedence
• CPC Class Codes: H02J 50/005 Mechanical details of housing or structure aiming to accommodate the power transfer means, e.g. mechanical integration of coils, antennas or transducers into emitting or receiving devices
• CPC Class Codes: H02J 50/10 using inductive coupling
• CPC Class Codes: H02J 50/27 characterised by the type of receiving antennas, e.g. rectennas
• CPC Class Codes: H02M 1/123 Suppression of common mode voltage or current
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H02M 7/23 arranged for operation in parallel H02M7/2176 takes precedence

Abstract

A rectifying circuit includes, in part, first and second NMOS transistors, an impedance matching network, and an RF block circuit. The source and gate terminals of the first NMOS transistor respectively receive the ground potential and a biasing voltage. The second NMOS transistor has a gate terminal coupled to the drain terminal of the first NMOS transistor, a drain terminal coupled to the gate terminal of the first NMOS transistor, and a source terminal receiving the ground potential. The impedance matching network is disposed between the antenna and the drain terminals of the first and second NMOS transistors. The RF block circuit is coupled between the drain terminals of the first and second NMOS transistors and the output terminal of the rectifying circuit. The RF block circuit is adapted to prevent the RF signal from flowing into the output terminal of the rectifying circuit.

Claims

1. A rectifying circuit adapted to rectify an RF signal supplied by an antenna receiving electromagnetic waves, the rectifying circuit comprising:

a first NMOS transistor having a source terminal receiving a ground potential and a gate terminal receiving a biasing voltage;

a second NMOS transistor having a gate terminal coupled to the drain terminal of the first NMOS transistor, a drain terminal coupled to the gate terminal of the first NMOS transistor, and a source terminal receiving the ground potential;

an impedance matching network disposed between the antenna and the drain terminals of the first and second NMOS transistors;

an RF block circuit coupled between the drain terminals of the first and second NMOS transistors and an output terminal of the rectifying circuit, said RF block circuit adapted to block the RF signal from arriving at the output terminal of the rectifying circuit;

a first capacitive element disposed between the gate terminal of the first NMOS transistor and the drain terminal of the second NMOS transistor; and

a second capacitive element disposed between the gate terminal of the second NMOS transistor and the drain terminal of the first NMOS transistor.

2. The rectifying circuit of claim 1 wherein said impedance matching network comprises a first inductive element coupled between the output terminal and the drain terminal of the first NMOS transistor, and a second inductive element coupled between the output terminal and the drain terminal of the second NMOS transistor.

3. The rectifying circuit of claim 2 wherein said RF block circuit comprises a capacitive element disposed between the output terminal and a ground terminal supplying the ground potential.

4. The rectifying circuit of claim 1 further comprising:

a biasing circuit supplying the biasing voltage to the gate terminals of the first and second NMOS transistors.

5. The rectifying circuit of claim 4 wherein said biasing circuit is a battery.

6. The rectifying circuit of claim 4 wherein said biasing circuit supplies the biasing voltage in response to an output voltage the biasing circuit senses at the output terminal.

7. The rectifying circuit of claim 4 wherein said rectifying circuit further comprises:

a first resistive element disposed between the biasing circuit and the gate terminal of the first NMOS transistor; and

a second resistive element disposed between the biasing circuit and the gate terminal of the second NMOS transistor.

8. The rectifying circuit of claim 1 wherein said first and second NMOS transistors are enhancement mode transistors.

9. The rectifying circuit of claim 1 wherein said first and second NMOS transistors are depletion mode transistors.

10. The rectifying circuit of claim 1 wherein said RF signal is applied between the drain terminals of the first and second NMOS transistors.

11. The rectifying circuit of claim 1 wherein said RF signal is applied between the drain terminal of the first NMOS transistor and a ground terminal supplying the ground potential.

12. The rectifying circuit of claim 4 wherein said rectifying circuit further comprises:

a first inductive element disposed between the biasing circuit and the gate terminal of the first NMOS transistor; and

a second inductive element disposed between the biasing circuit and the gate terminal of the second NMOS transistor.

13. A rectifying circuit adapted to rectify an RF signal supplied by an antenna receiving electromagnetic waves, the rectifying circuit comprising:

an NMOS transistor having a source terminal receiving a ground potential;

an impedance matching network disposed between the antenna and the drain terminal of the NMOS transistor;

an RF block circuit coupled between the drain terminal of the NMOS transistor and an output terminal of the rectifying circuit, said RF block circuit adapted to block the RF signal from arriving at the output terminal of the rectifying circuit; and

a gate driver circuit driving a gate terminal of the NMOS transistor in response to an output voltage present at the output terminal of the rectifying circuit.

14. The rectifying circuit of claim 13 wherein said impedance matching network comprises a portion of a transformer having a first output terminal coupled to the drain terminal of the NMOS transistor and a second output terminal coupled to the gate terminal of the NMOS transistor, said first and second output terminals of the transformer supplying signals that are 180°

out-of-phase with respect to one another.

15. The rectifying circuit of claim 14 wherein said RF block circuit comprises:

an inductive element disposed between the drain terminal of the NMOS transistor and the output terminal; and

a capacitive element disposed between the output terminal and a ground terminal supplying the ground potential.

16. The rectifying circuit of claim 14 wherein said gate driver circuit drives the gate terminal of the NMOS transistor via a second input terminal of the transformer.

17. A method of rectifying an RF signal delivered by an antenna, said antenna delivering the RF signal in response to electromagnetic waves incident thereon, the method comprising:

applying a biasing voltage to a gate terminal of a first NMOS transistor having a source terminal receiving a ground potential;

applying the biasing voltage to a gate terminal of a second NMOS transistor having a gate terminal coupled to the drain terminal of the first NMOS transistor, a drain terminal coupled to the gate terminal of the first NMOS transistor, and a source terminal receiving the ground potential;

matching an impedance of the antenna to an impedance of the drain terminals of the first and second NMOS transistor; and

blocking the RF signal from arriving at an output terminal carrying the rectified signal.

18. The method of claim 17 further comprising:

applying the biasing voltage to the gate terminal of the first NMOS transistor via a first capacitive element; and

applying the biasing voltage to the gate terminal of the second NMOS transistor via a second capacitive element.

19. The method of claim 17 wherein said impedance matching comprises matching the impedance via a first inductive element coupled between the output terminal and the drain terminal of the first NMOS transistor, and a second inductive element coupled between the output terminal and the drain terminal of the second NMOS transistor.

20. The method of claim 19 wherein said blocking of the RF signal comprises blocking of the RF signal via a capacitive element disposed between the output terminal and a ground terminal supplying the ground potential.

21. The method of claim 17 further comprising:

supplying the biasing voltage via a battery.

22. The method of claim 17 further comprising:

supplying the biasing voltage in response to a voltage present at the output terminal.

23. The method of claim 17 further comprising:

supplying the biasing voltage to the gate terminal of the first NMOS transistor via a first resistive element; and

supplying the biasing voltage to the gate terminal of the second NMOS transistor via a second resistive element.

24. The method of claim 17 wherein said first and second NMOS transistors are enhancement mode transistors.

25. The method of claim 17 wherein said first and second NMOS transistors are depletion mode transistors.

26. The method of claim 17 further comprising:

applying the RF signal between the drain terminals of the first and second NMOS transistors.

27. The method of claim 17 further comprising:

applying the RF signal between the drain terminal of the first transistor NMOS transistor and a ground terminal supplying the ground potential.

28. The method of claim 17 further comprising:

supplying the biasing voltage to the gate terminal of the first NMOS transistor via a first inductive element; and

supplying the biasing voltage to the gate terminal of the second NMOS transistor via a second inductive element.

29. A method of rectifying an RF signal delivered by an antenna, said antenna delivering the RF signal in response to electromagnetic waves incident thereon, the method comprising:

driving a gate terminal of an NMOS transistor in response to the rectified signal;

applying a ground potential to a source terminal of the NMOS transistor;

matching an impedance of the antenna to an impedance of the drain terminal of the NMOS transistor;

blocking the RF signal from arriving at an output terminal carrying the rectified signal; and

matching the impedance of the antenna and the drain terminal of the NMOS transistor via a matching network comprising a portion of a transformer having a first output terminal coupled to the drain terminal of the NMOS transistor and a second output terminal coupled to the gate terminal of the NMOS transistor, said first and second output terminals of the transformer supplying signals that are 180°

out-of-phase with respect to one another.

30. The method of claim 29 further comprising:

blocking the RF signal via an inductive element disposed between the drain terminal of the first NMOS transistor and the output terminal, and a capacitive element disposed between the output terminal and a ground terminal supplying the ground potential.

31. The method of claim 29 further comprising:

driving the gate terminal of the NMOS transistor via a second input terminal of the transformer.