Direct current link circuit

• US 10,007,288 B2
• Filed: 03/21/2017
• Issued: 06/26/2018
• Est. Priority Date: 03/05/2012
• Status: Active Grant

• Current Assignee: Solaredge Technologies Incorporated
• Original Assignee: Solaredge Technologies Incorporated
• Inventors: Gazit, Meir, Lubomirsky, Vadim
• Primary Examiner(s): Pham, Emily P
• Application Number:
  US15/464,850
• Publication Number:
  US 20170255218A1
• Time in Patent Office: 462 Days
• CPC Class Codes: G05F 3/08 wherein the variable is dc
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 7/44 by static converters
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02E 10/56 Power conversion systems, e.g. maximum power point trackers

Abstract

An electronic circuit for converting power from a floating source of DC power to a dual direct current (DC) output is disclosed. The electronic circuit may include a positive input terminal and a negative input terminal connectible to the floating source of DC power. The dual DC output may connectible to the input of an inverter. A positive output terminal connected to the positive input terminal of the inverter and a negative output terminal and a ground terminal which may be connected to the input of the inverter. A series connection of a first power switch and a second power switch connected across the positive input terminal and the negative input terminal. A negative return path may include a first diode and a second diode connected between the negative input terminal and the negative output terminal. A resonant circuit may connect between the series connection and the negative return path.

Claims

1. An electronic circuit comprising:

positive and negative input terminals configured to be connected across a floating source of direct current (DC) power;

positive and negative output terminals;

first and second field effect transistors each comprising an integral diode, wherein the first and second field effect transistors are connected in series across the positive and negative input terminals, and wherein a connection point between the first and second field effect transistors forms a first node;

first and second diodes connected in series, wherein a connection point between the first and second diodes forms a second node;

a first resonant circuit connected in series between the first and second nodes, wherein, when the first field effect transistor is closed and the second field effect transistor is open, the first resonant circuit is connected across the positive and negative input terminals through the first diode, and wherein, when the first field effect transistor is open and the second field effect transistor is closed, the positive and negative output terminals and the first resonant circuit are connected in series across the positive and negative input terminals through the second diode;

third and fourth field effect transistors each comprising an integral diode, wherein the third and fourth field effect transistors are connected in series across the positive and negative input terminals, and wherein a connection point between the third and fourth field effect transistors forms a third node;

third and fourth diodes connected in series, wherein a connection point between the third and fourth diodes forms a fourth node; and

a second resonant circuit connected in series between the third and fourth nodes, wherein, when the third field effect transistor is closed and the fourth field effect transistor is open, the second resonant circuit is connected across the positive and negative input terminals through the third diode, wherein, when the third field effect transistor is open and the fourth field effect transistor is closed, the positive and negative output terminals and the second resonant circuit are connected in series across the positive and negative input terminals through the fourth diode, wherein the first and fourth field effect transistors are configured to be opened and closed together, and wherein the second and third field effect transistors are configured to be opened and closed together.

2. The electronic circuit of claim 1, wherein a cathode of the first diode is connected to the negative input terminal, an anode of the second diode is connected to the negative output terminal, and an anode of the first diode and a cathode of the second diode are connected to the second node.

3. The electronic circuit of claim 1, wherein an anode of the first diode is connected to the positive input terminal, a cathode of the second diode is connected to the positive output terminal, and a cathode of the first diode and an anode of the second diode are connected to the second node.

4. The electronic circuit of claim 1, further comprising a charge storage device connected across the positive and negative input terminals.

5. The electronic circuit of claim 1, wherein the first resonant circuit comprises an inductor and a capacitor that are connected in series between the first and second nodes.

6. The electronic circuit of claim 1, further comprising:

a ground output terminal;

a first capacitor connected between the positive and ground output terminals;

a second capacitor connected between the negative and ground output terminals; and

an inverter comprising a positive inverter input terminal connected to the positive output terminal, a negative inverter input terminal connected to the negative output terminal, and a ground inverter terminal connected to the ground output terminal.

7. The electronic circuit of claim 1, further comprising first and second drive circuits configured to alternately gate the first and second field effect transistors with a pulse width modulation (PWM) cycle such that the first field effect transistor is closed while the second field effect transistor is open during a first half of the PWM cycle and the second field effect transistor is closed while the first field effect transistor is open during a second half of the PWM cycle.

8. The electronic circuit of claim 7, wherein the first and second drive circuits are configured to alternately gate, with the PWM cycle, the first and second field effect transistors with less than a fifty percent duty cycle.

9. The electronic circuit of claim 7, wherein the first and second drive circuits are configured to open and close the first and second field effect transistors while substantially zero current flows, respectively, through the first and second field effect transistors.

10. A method comprising:

connecting a floating source of a direct current (DC) power across positive and negative input terminals of a circuit, the circuit comprising;

a dual DC output comprising positive and negative output terminals referenced to a ground output terminal;

first and second field effect transistors each comprising an integral diode, wherein the first and second field effect transistors are connected in series across the positive and negative input terminals, and wherein a connection point between the first and second field effect transistors forms a first node,

first and second diodes connected in series, wherein a connection point between the first and second diodes forms a second node,

a first resonant circuit connected in series between the first and second nodes, wherein, when the first field effect transistor is closed and the second field effect transistor is open, the first resonant circuit is connected across the positive and negative input terminals through the first diode, and wherein, when the first field effect transistor is open and the second field effect transistor is closed, the positive and negative output terminals and the first resonant circuit are connected in series across the positive and negative input terminals through the second diode,

third and fourth field effect transistors each comprising an integral diode, wherein the third and fourth field effect transistors are connected in series across the positive and negative input terminals, and wherein a connection point between the third and fourth field effect transistors forms a third node,

third and fourth diodes connected in series, wherein a connection point between the third and fourth diodes forms a fourth node, and

a second resonant circuit connected in series between the third and fourth nodes, wherein, when the third field effect transistor is closed and the fourth field effect transistor is open, the second resonant circuit is connected across the positive and negative input terminals through the third diode, wherein, when the third field effect transistor is open and the fourth field effect transistor is closed, the positive and negative output terminals and the second resonant circuit are connected in series across the positive and negative input terminals through the fourth diode, wherein the first and fourth field effect transistors are configured to be opened and closed together, and wherein the second and third field effect transistors are configured to be opened and closed together; and

alternately gating the first and second field effect transistors such that the first field effect transistor is closed and the second field effect transistor is open during a first phase of a pulse width modulation (PWM) cycle thereby charging the first resonant circuit from the floating source of DC power, and such that the first field effect transistor is open and the second field effect transistor is closed during a second phase of the PWM cycle thereby discharging the first resonant circuit to provide converted power to a load connected to the positive output terminal, the negative output terminal, and the ground output terminal.

11. The method of claim 10, wherein:

a cathode of the first diode is connected to the negative input terminal, an anode of the second diode is connected to the negative output terminal, and an anode of the first diode and a cathode of the second diode are connected to the second node.

12. The method of claim 10, wherein:

an anode of the first diode is connected to the positive input terminal, a cathode of the second diode is connected to the positive output terminal, and a cathode of the first diode and an anode of the second diode are connected to the second node.

13. The method of claim 10, wherein the load comprises an inverter, the method further comprising:

inverting, by the inverter, the converted power.

14. The method of claim 10, further comprising

alternately gating, with the PWM cycle, the first and second field effect transistors with less than a fifty percent pulse width modulation duty cycle.

15. The method of claim 10, further comprising

alternately gating, with the PWM cycle, the first and second field effect transistors such that each of the first and second field effect transistors opens and closes while substantially zero current flows, respectively, through the first and second field effect transistors.

16. An electronic circuit comprising:

positive and negative input terminals configured to be connected across a floating source of direct current (DC) power;

positive and negative output terminals;

first and second field effect transistors connected in series across the positive and negative input terminals, wherein a connection point between the first and second field effect transistors forms a first node;

first and second diodes connected in series, wherein a connection point between the first and second diodes forms a second node;

a first resonant circuit connected in series between the first and second nodes, wherein, when the first field effect transistor is closed and the second field effect transistor is open, the first resonant circuit is connected across the positive and negative input terminals through the first diode, and wherein, when the first field effect transistor is open and the second field effect transistor is closed, the positive and negative output terminals and the first resonant circuit are connected in series across the positive and negative input terminals through the second diode;

third and fourth field effect transistors connected in series across the positive and negative input terminals, wherein a connection point between the third and fourth field effect transistors forms a third node;

third and fourth diodes connected in series, wherein a connection point between the third and fourth diodes forms a fourth node; and

a second resonant circuit connected in series between the third and fourth nodes, wherein, when the third field effect transistor is closed and the fourth field effect transistor is open, the second resonant circuit is connected across the positive and negative input terminals through the third diode, wherein, when the third field effect transistor is open and the fourth field effect transistor is closed, the positive and negative output terminals and the second resonant circuit are connected in series across the positive and negative input terminals through the fourth diode, wherein gates of the first and fourth field effect transistors are configured to be driven by a first drive signal, and wherein gates of the second and third field effect transistors are configured to be driven by a second drive signal.

17. The electronic circuit of claim 16, further comprising one or more drive circuits configured to generate the first drive signal and the second drive signal, wherein the one or more drive circuits are configured to generate the first and second drive signals such that the first, second, third, and fourth field effect transistors perform zero-current switching.

18. The electronic circuit of claim 16, further comprising an inverter connected to the positive and negative output terminals.

19. The electronic circuit of claim 16, wherein a cathode of the first diode is connected to the negative input terminal, an anode of the second diode is connected to the negative output terminal, and an anode of the first diode and a cathode of the second diode are connected to the second node.

20. The electronic circuit of claim 16, wherein an anode of the first diode is connected to the positive input terminal, a cathode of the second diode is connected to the positive output terminal, and a cathode of the first diode and an anode of the second diode are connected to the second node.