Integrated battery safety interlock

• US 10,014,700 B2
• Filed: 04/28/2016
• Issued: 07/03/2018
• Est. Priority Date: 02/04/2016
• Status: Active Grant

• Current Assignee: CPS Technology Holdings, LLC
• Original Assignee: Johnson Controls Technology Company (Johnson Controls International plc)
• Inventors: Tosch, Charles S.
• Primary Examiner(s): Kaplan, Hal
• Application Number:
  US15/141,438
• Publication Number:
  US 20170229884A1
• Time in Patent Office: 796 Days
• Field of Search: 307 91, 307 101, 307 107, 307131
• CPC Class Codes: B60L 3/0046 relating to electric energy storage systems, e.g. batteries or capacitors
• CPC Class Codes: B60L 3/04 Cutting off the power supply under fault conditions protective devices and circuit arrangements in general H01H; H02H
• CPC Class Codes: B60L 58/10 for monitoring or controlling batteries
• CPC Class Codes: B60L 58/26 by cooling
• CPC Class Codes: G01R 31/007 using microprocessors or computers
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: H01M 10/052 Li-accumulators
• CPC Class Codes: H01M 10/06 Lead-acid accumulators semi-lead accumulators H01M10/20
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H01M 10/482 for several batteries or cells simultaneously or sequentially
• CPC Class Codes: H01M 2010/4271 Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
• CPC Class Codes: H02J 7/0029 with safety or protection devices or circuits
• CPC Class Codes: H02J 7/0031 using battery or load disconnect circuits H02J9/002 takes precedence
• CPC Class Codes: H02J 7/0048 Detection of remaining charge capacity or state of charge [SOC]
• CPC Class Codes: H02J 7/005 Detection of state of health [SOH]
• CPC Class Codes: H02J 7/14 for charging batteries from dynamo-electric generators driven at varying speed, e.g. on vehicle
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries

Abstract

The present disclosure includes a battery system that may include a first terminal and a second terminal electrically coupled to an electronic component. The system may also include a current source electrically coupled to the first terminal. The system may also include a control system that may direct an asynchronous current from the current source to the first terminal according to a pattern and receive a current signal status from a current detector. The current signal status is associated with a second current received via the second terminal. The control system may disconnect the electronic component from the first terminal or the second terminal when the current signal status does not correspond to the pattern.

Claims

1. A battery system, comprising:

a first terminal and a second terminal configured to electrically couple to an electronic component;

a current source electrically coupled to the first terminal;

a control system configured to;

direct an asynchronous current from the current source to the first terminal according to a pattern;

receive a current signal status from a current detector, wherein the current signal status is associated with a second current received via the second terminal; and

disconnect the electronic component from the first terminal or the second terminal when the current signal status does not correspond to the pattern.

2. The battery system of claim 1, wherein the pattern is configured to indicate when the current source is activated and deactivated.

3. The battery system of claim 1, wherein the asynchronous current alternates between at least two current values based on a current signal comprising a second pattern in which the asynchronous current alternates between the at least two current values.

4. The battery system of claim 3, wherein the at least two current values comprises 10 mA and 20 mA.

5. The battery system of claim 1, wherein the control system is configured to send a disable signal to an input/output (I/O) component when the current signal status does not correspond to the pattern, wherein the I/O component is configured to break a connection path between the electronic component and first terminal or the second terminal based on the disable signal.

6. The battery system of claim 5, wherein the control system is configured to send the disable signal when the current signal status does not correspond to the pattern for more than a period of time.

7. The battery system of claim 6, wherein the period of time comprises 50 ms.

8. The battery system of claim 5, wherein the I/O disable component comprises a switch configured to disconnect the electronic component from the first terminal or the second terminal.

9. The battery system of claim 1, comprising a hardware filter configured to:

receive a delta signal from the current detector, wherein the delta signal indicates whether the current signal status corresponds to the pattern; and

disconnect the electronic component from the first terminal or the second terminal when the current signal status does not correspond to the pattern.

10. The battery system of claim 9, wherein the hardware filter is configured to disconnect the electronic component from the first terminal or the second terminal when the current signal status does not correspond to the pattern for more than a period of time.

11. The battery system of claim 9, comprising a hardware failsafe circuit configured to receive a disconnect signal from the hardware filter when the delta signal indicates that the current signal status does not correspond to the pattern, wherein the disconnect signal is configured to cause the electronic component to be disconnected from the first terminal or the second terminal.

12. The battery system of claim 11, comprising the hardware failsafe circuit configured to receive a disconnect signal from the hardware filter when the delta signal indicates that the current signal status does not correspond to the pattern for longer than a period of time, wherein the disconnect signal is configured to cause the electronic component to be disconnected from the first terminal or the second terminal.

13. The battery system of claim 1, comprising the current detector, wherein the current detector comprises a resistor, and wherein a voltage drop across the resistor is associated with the current signal status.

14. A non-transitory computer-readable medium comprising computer-executable instructions configured to cause a processor to:

cause a current source to output an asynchronous current to a first terminal of a battery module according to a pattern;

receive a current signal status from a current detector electrically coupled to a second terminal of the battery module, wherein the current signal status is associated with a second current received via the second terminal; and

send a disable signal to an input/output (I/O) component when the current signal status does not correspond to the pattern, wherein the disable signal is configured to cause the I/O component to disconnect an electronic component electrically coupled to the first terminal or the second terminal from the first terminal or the second terminal.

15. The non-transitory computer-readable medium of claim 14, wherein the pattern is configured to indicate when the current source is activated and deactivated.

16. The non-transitory computer-readable medium of claim 14, wherein the processor is configured to send a current signal to the current source, wherein the current signal comprising a second pattern in which the asynchronous current alternates between two current values.

17. The non-transitory computer-readable medium of claim 14, wherein the current signal status comprises a voltage waveform that is associated with one or more current values of the second current.

18. The non-transitory computer-readable medium of claim 17, wherein the voltage waveform corresponds to a voltage across a resistor within the current detector.

19. The battery module of claim 18, wherein the computer-executable instructions are configured to cause the processor to send the disable signal to the I/O component when the current signal status does not correspond to the pattern for more than a period of time.

20. A system, comprising:

a battery;

a battery control unit communicatively coupled to the battery, wherein the battery control unit comprises;

a first terminal and a second terminal configured to electrically couple to an electronic component;

a current source electrically coupled to the first terminal;

a failsafe circuit coupled to the second terminal; and

a processor configured to;

send an activation pattern to the current source configured to output a first current according to the activation pattern to the first terminal, wherein the first terminal is configured to serially couple to the electronic component; and

send a current signal to the current source, wherein the current signal comprises a current pattern that indicates at least two different current values for the first current output by the current source;

wherein the failsafe circuit is configured to;

receive a signal status from a current detector configured to electrically couple to the second terminal, wherein the signal status comprises a waveform indicating one or more current values of a second current received via the second terminal; and

send a disable signal to an input/output (I/O) component when the signal status does not match the activation pattern and the current signal, wherein the disable signal is configured to cause the I/O component to disconnect the electronic component from the first terminal or the second terminal.

21. The system of claim 20, wherein the failsafe circuit is configured to send the disable signal when the signal status does not match the activation pattern and the current signal for more than a period of time.

22. The system of claim 20, wherein the processor is configured to generate the activation pattern according to a random function.

23. The system of claim 20, wherein the failsafe circuit is configured to receive a delta signal from the current detector, wherein the delta signal indicates whether the signal status does not match the activation pattern and the current signal.