System on a chip with always-on processor

• US 10,031,000 B2
• Filed: 08/13/2014
• Issued: 07/24/2018
• Est. Priority Date: 05/29/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Tripathi, Brijesh, Keil, Shane J., Gulati, Manu, Cho, Jung Wook, Machnicki, Erik P., Herbeck, Gilbert H., Millet, Timothy J., de Cesare, Joshua P., Dalal, Anand
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Sabur, Alia
• Application Number:
  US14/458,885
• Publication Number:
  US 20150346001A1
• Time in Patent Office: 1,441 Days
• Field of Search: None
• CPC Class Codes: A61G 3/061 using ramps
• CPC Class Codes: B60P 1/433 the loading floor or a part thereof being movable to form the ramp
• CPC Class Codes: G01D 9/00 Recording measured values
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Claims

1. An integrated circuit comprising:

a plurality of components, wherein the plurality of components includes a central processing unit (CPU) processor and a memory controller that couples to a first memory during use; and

a first component coupled to the plurality of components and coupled to at least one sensor in a system that includes the integrated circuit during use, wherein;

the first component includes a first processor, a sensor capture circuit, and a second memory;

the first component is configured to remain powered on while the plurality of components are powered off;

the sensor capture circuit is configured to capture a plurality of samples of sensor data from the sensor and write the plurality of samples to the second memory;

the first processor is configured to detect a predetermined state in the captured plurality of samples of sensor data in the second memory during a time that the plurality of components are powered down;

the first component is configured to cause the memory controller and a communication path to the memory controller from the first component to be powered on in response to the captured plurality of samples filling to a threshold level in the second memory and the first processor detecting a lack of the predetermined state in the captured plurality of samples; and

the first component is configured to transfer the plurality of samples of sensor data from the second memory to the first memory for processing by the CPU processor, wherein the transfer is accomplished while the CPU processor remains powered off responsive to the first processor detecting the lack of the predetermined state.

2. The integrated circuit as recited in claim 1 wherein the first processor is configured to filter the captured plurality of samples of sensor data in the second memory.

3. The integrated circuit as recited in claim 2 wherein the first component is configured to detect the predetermined state during the filtering.

4. The integrated circuit as recited in claim 1 wherein the first component is configured to operate at a plurality of power states, and wherein a first power state of the plurality of power states includes the sensor capture circuit being powered on and capturing sensor data while the first processor is inactive.

5. The integrated circuit as recited in claim 4 wherein a second power state of the plurality of power states includes the first processor being active to perform the processing.

6. The integrated circuit as recited in claim 5 wherein the first component is configured to transition from the first power state to the second power state responsive to the captured sensor data in the second memory reaching a predetermined amount.

7. The integrated circuit as recited in claim 4 wherein a second power state of the plurality of power states includes the sensor capture circuit and the first processor being inactive.

8. The integrated circuit as recited in claim 7 wherein the first component is configured to transition from the second power state to the first power state responsive to sensor data being available to read.

9. The integrated circuit as recited in claim 1 wherein the first component is configured to cause the plurality of components to be powered on in response to the first processor detecting the predetermined state.

17. The integrated circuit as recited in claim 9 wherein the first component is configured to transfer the captured plurality of samples, including the predetermined state, from the second memory to the first memory.

10. A method comprising:

powering a first component of a plurality of components in an integrated circuit during a time that a remainder of the plurality of components are powered down; and

during the time that the remainder of the plurality of components are powered down, the first component;

capturing a plurality of samples of sensor data from at least one sensor coupled to the integrated circuit using a sensor capture circuit in the first component and a first memory in the first component to store the captured plurality of samples, wherein a first processor in the first component is powered down during the capturing of the plurality of samples;

powering up the first processor responsive to capturing the plurality of samples;

filtering the captured plurality of samples of sensor data in the first processor, wherein the filtering includes attempting to detect a predetermined state in the captured plurality of samples;

powering up a memory controller in the plurality of components and a communication path to the memory controller responsive to the captured plurality of samples filling to a threshold level in the first memory and further responsive to detecting a lack of the predetermined state during the filtering; and

transferring the captured plurality of samples from the first memory to a second memory controlled by the memory controller responsive to detecting the lack of the predetermined state, wherein one of the plurality of components comprises a central processing unit (CPU) processor configured to process the plurality of samples in the second memory, wherein the transferring is performed while the CPU processor remains powered down.

11. The method as recited in claim 10 wherein the first component is configured to operate at a plurality of power states, and wherein the capturing occurs at a first power state of the plurality of power states, and wherein the filtering occurs at a second power state of the plurality of states, wherein the method further comprises:

detecting that the captured plurality of samples of sensor data is ready for filtering; and

transitioning from the first power state to the second power state responsive to the detecting.

12. The method as recited in claim 11 wherein the first component is further configured to operate at a third power state when idle, wherein the method further comprises:

detecting that a first sample of the plurality of samples sensor data is ready for capturing; and

transitioning from the third power state to the first power state responsive to the detecting.

13. The method as recited in claim 12 wherein the first power state comprises the sensor capture circuit being active and the first processor within the first component being inactive, wherein transitioning to the second power state comprises activating the first processor to perform the filtering.

14. The method as recited in claim 13 wherein the third power state comprises the first processor and the sensor capture circuit being inactive, wherein transitioning to the first power state comprises activating the sensor capture circuit.

15. The method as recited in claim 12 further comprising transitioning from the first power state to the third power state responsive to completing the capturing of the sensor data.

16. The method as recited in claim 12 further comprising transitioning from the second power state to one of the first power state and the third power state responsive to completing the filtering.

23. The method as recited in claim 10 further comprising powering up the remainder of plurality of components responsive to detecting a predetermined state in the captured plurality of samples of sensor data during the filtering.

18. A system comprising:

at least one sensor;

an external memory; and

a system on a chip (SOC) comprising a central processing unit (CPU) complex, a memory controller coupled to the external memory, and a component that is powered on when a remainder of the SOC, including the CPU complex and the memory controller, is powered off, wherein the component is coupled to the sensor and is configured to capture data from the sensor and filter the captured data during a time that the remainder of the SOC is powered off, wherein the component comprises a first processor, a second memory coupled to the first processor, and a sensor capture circuit coupled to the second memory, wherein the sensor capture circuit is configured to capture a plurality of samples of sensor data from the sensor and to write the captured plurality of samples to the second memory while the first processor is powered down, and wherein the first processor is configured to wake to filter the captured plurality of samples of sensor data in the second memory, wherein the component is configured to transfer the plurality of samples of sensor data from the second memory to the external memory for processing by the CPU complex, wherein the transfer occurs while the CPU complex remains powered off in the case that the captured plurality of samples fill to a threshold level in the second memory and the first processor detecting a lack of a predetermined state in the plurality of samples of sensor data, wherein detecting the predetermined state causes the component to wake the CPU complex.

19. The system as recited in claim 18 wherein the sensor is an accelerometer.

20. The system as recited in claim 18 wherein the sensor is a gyroscope.

21. The system as recited in claim 18 wherein the component supports a plurality of power states, wherein different power states of the plurality of power states are used for the data capture and for the filter of the captured data.

22. The system as recited in claim 21 wherein the component is configured to determine that the remainder of the SOC is to be powered up, and wherein the component is configured to cause the SOC to power up responsive to determining that the remainder of the SOC is to power up.