Semiconductor device having recessed edges and method of manufacture

• US 10,032,746 B2
• Filed: 09/07/2016
• Issued: 07/24/2018
• Est. Priority Date: 09/05/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US15/258,933
• Publication Number:
  US 20160379956A1
• Time in Patent Office: 685 Days
• CPC Class Codes: H01L 21/31 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After treatment of these layers; Selection of materials for these layers
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/786 the substrate being other than a semiconductor body, e.g. insulating body
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/31 : characterised by the arrangement or shape
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A device and method of manufacture is provided that utilize recessed regions along a package edge. For example, in an integrated fan-out package, the dielectric layers, e.g., the polymer layers, of the redistribution layers are removed along the scribe line such that after singulation the dielectric layers are recessed back from the edges of the die. The corner regions may be recessed further. The recessed regions may be triangular, rounded, or other shape. In some embodiments one or more of the corner regions may be recessed further relative to the remaining corner regions. The redistribution layers may be recessed along one or both of the front side redistribution layers and the backside redistribution layers.

Claims

1. A method comprising:

providing a workpiece, the workpiece having intersecting scribe lines;

forming one or more first dielectric layers over a first side of the workpiece, the first dielectric layers recessed a first distance from the scribe lines at a first location near a first intersection of the scribe lines, the first dielectric layers recessed a second distance from the scribe lines at a second location, the second location being further from the first intersection than the first location, the first distance being greater than the second distance, wherein the forming the first dielectric layers comprises recessing a first corner a greater distance than a second corner; and

singulating the workpiece along the scribe lines.

2. The method of claim 1, wherein the forming the first dielectric layers comprises forming rounded corners near intersecting scribe lines.

3. The method of claim 1, wherein the forming the first dielectric layers comprises forming tapered corners near intersecting scribe lines.

4. The method of claim 1, wherein the forming the first dielectric layers comprises forming a plurality of dielectric layers, the forming the plurality of dielectric layers comprising:

forming a dielectric layer;

patterning the dielectric layer to remove portions of the dielectric layer along scribe lines; and

after the patterning, repeating the forming and the patterning one or more times.

20. The method of claim 1, further comprising forming one of more conductive layers in the one or more first dielectric layers.

5. A method comprising:

placing a first die over a carrier substrate;

forming a molding compound over the carrier substrate;

forming one or more first redistribution layers over the molding compound and the first die, the one or more first redistribution layers comprising one or more first dielectric layers and one or more first conductive layers;

removing the one or more first dielectric layers in a scribe line, the molding compound in the scribe line remaining after removing the one or more first dielectric layers; and

singulating the first die along the scribe line, wherein an edge of the one or more first redistribution layers being recessed from an edge of the molding compound after singulating.

6. The method of claim 5, further comprising forming one or more second redistribution layers over the carrier substrate, wherein placing the first die over the carrier substrate comprises placing the first die over the one or more second redistribution layers, the one or more second redistribution layers being interposed between the first die and the carrier substrate.

7. The method of claim 6, wherein after singulating the first die along the scribe line, the edge of the one or more first redistribution layers being recessed from an edge of the of the one or more second redistribution layers in a plan view.

8. The method of claim 6, wherein after singulating the first die along the scribe line, an edge of the one or more second redistribution layers being recessed from an edge of the molding compound in a plan view.

9. The method of claim 5, wherein removing the one or more first dielectric layers comprises patterning the one or more first dielectric layers to have non-perpendicular corners in a plan view.

10. The method of claim 9, wherein the one or more first dielectric layers comprises rounded corners near intersecting scribe lines.

11. The method of claim 9, wherein the removing the one or more first dielectric layers comprises forming tapered corners near intersecting scribe lines.

12. The method of claim 9, wherein the removing the one or more first dielectric layers comprises recessing a first corner a greater distance than a second corner.

13. A method comprising:

placing a first die and a second die over a carrier substrate;

forming one or more conductive vias over the carrier substrate;

forming a molding compound over the carrier substrate, the molding compound extending along sidewalls of the one or more conductive vias, the first die, and the second die;

forming one or more first redistribution layers over a first side of the molding compound, first die and the second die, the one or more first redistribution layers comprising one or more first dielectric layers and one or more first conductive layers;

removing at least a portion of the one or more first dielectric layers in a scribe line interposed between the first die and the second die to form a recess, the molding compound being exposed along a bottom of the recess; and

singulating the first die from the second die along the scribe line, the one or more first redistribution layers being recessed by a first distance from a sidewall of the molding compound in a sidewall region, the one or more first redistribution layers being recessed from the sidewall of the molding compound by a second distance along a corner region, the second distance being greater than the first distance.

14. The method of claim 13, further comprising:

forming one or more second redistribution layers extending over a second side of the molding compound, first die and the second die opposite the first side, the one or more second redistribution layers being recessed from the sidewall of the molding compound by a third distance along the sidewall region, the one or more second redistribution layers being recessed from the sidewall of the molding compound by a fourth distance along the corner region, the fourth distance being greater than the third distance.

15. The method of claim 13, wherein a corner of the one or more first redistribution layers is rounded.

16. The method of claim 13, wherein a corner of the one or more first redistribution layers is tapered.

17. The method of claim 13, wherein each corner of the one or more first redistribution layers is recessed a similar amount.

18. The method of claim 13, wherein at least one corner of the one or more first redistribution layers are recessed a different amount than another of the corners.

19. The method of claim 13, wherein first diagonal corners of the one or more first redistribution layers are recessed third distance, and wherein second diagonal corners of the one or more first redistribution layers are recessed a fourth distance, the third distance different than the fourth distance.