Systems, apparatuses, and methods for performing delta decoding on packed data elements

• US 10,037,209 B2
• Filed: 01/30/2017
• Issued: 07/31/2018
• Est. Priority Date: 12/28/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ould-Ahmed-Vall, Elmoustapha, Willhalm, Thomas, Drysdale, Tracy Garrett
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US15/419,888
• Publication Number:
  US 20170139715A1
• Time in Patent Office: 547 Days
• Field of Search: None
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence

Abstract

Systems, apparatuses, and methods for performing delta decoding on packed data elements of a source and storing the results in packed data elements of a destination using a single packed delta decode instruction are described. A processor may include a decoder to decode an instruction, and execution unit to execute the decoded instruction to calculate for each packed data element position of a source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of a destination operand, and for each calculated value, store the value into a corresponding packed data element position of the destination operand.

Claims

1. A method comprising:

decoding a single instruction into a decoded single instruction with a decoder of a processor; and

executing, in an execution unit of the processor, the decoded single instruction that includes a source operand having a plurality of packed data elements and a destination operand to calculate for each packed data element position of the source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.

2. The method of claim 1, wherein the source and destination operands are vector registers.

3. The method of claim 2, wherein the vector registers are 128-bits in size.

4. The method of claim 2, wherein the vector registers are 256-bits in size.

5. The method of claim 2, wherein the vector registers are 512-bits in size.

6. The method of claim 1, wherein the packed data elements are 64-bits in size.

7. The method of claim 1, wherein the values are instead calculated by adding all of the packed data elements of the source operand together to create a sum value, storing that sum value in a last packed data element position of the destination operand, and, for each packed data element position other than the last packed data element position, subtracting all data elements of the source operand that come from packed data element positions of greater significance from the sum value and storing that result in a corresponding packed data element position of the destination operand.

8. An apparatus comprising:

a decoder to decode a single instruction that includes a source operand having a plurality of packed data elements and a destination operand into a decoded single instruction; and

an execution unit to execute the decoded single instruction to calculate for each packed data element position of the source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.

9. The apparatus of claim 8, further comprising:

a plurality of vector registers, wherein the source and destination operands are vector registers.

10. The apparatus of claim 9, wherein the vector registers are 128-bits in size.

11. The apparatus of claim 9, wherein the vector registers are 256-bits in size.

12. The apparatus of claim 9, wherein the vector registers are 512-bits in size.

13. The apparatus of claim 8, wherein the packed data elements are 64-bits in size.

14. The apparatus of claim 8, wherein the execution unit is to instead calculate values by adding all of the packed data elements of the source operand together to create a sum value, storing that sum value in a last packed data element position of the destination operand, and, for each packed data element position other than the last packed data element position, subtracting all data elements of the source operand that come from packed data element positions of greater significance from the sum value and store that result in a corresponding packed data element position of the destination operand.

15. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

decoding a single instruction into a decoded single instruction with a decoder of a processor; and

executing, in an execution unit of the processor, the decoded single instruction that includes a source operand having a plurality of packed data elements and a destination operand to calculate for each packed data element position of the source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of the destination operand, and for each calculated value, store the value into a packed data element position of the destination operand that corresponds to the packed data element position of the source operand.

16. The non-transitory machine readable medium of claim 15, wherein the source and destination operands are vector registers.

17. The non-transitory machine readable medium of claim 16, wherein the vector registers are 256-bits in size.

18. The non-transitory machine readable medium of claim 16, wherein the vector registers are 512-bits in size.

19. The non-transitory machine readable medium of claim 15, wherein the packed data elements are 64-bits in size.

20. The non-transitory machine readable medium of claim 15, wherein the values are instead calculated by adding all of the packed data elements of the source operand together to create a sum value, storing that sum value in a last packed data element position of the destination operand, and, for each packed data element position other than the last packed data element position, subtracting all data elements of the source operand that come from packed data element positions of greater significance from the sum value and storing that result in a corresponding packed data element position of the destination operand.