Migration of executing processes

• US 10,042,621 B2
• Filed: 08/08/2013
• Issued: 08/07/2018
• Est. Priority Date: 08/08/2013
• Status: Active Grant

• Current Assignee: Invincible IP LLC (IP Edge LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Kruglick, Ezekiel, Fine, Kevin S.
• Primary Examiner(s): Bullock, Jr., Lewis A
• Assistant Examiner(s): Ashley, Bruce S
• Application Number:
  US14/379,630
• Publication Number:
  US 20160216951A1
• Time in Patent Office: 1,825 Days
• Field of Search: None
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 8/41 Compilation
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4552 Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence

Abstract

In one example embodiment, live migration in a datacenter may include JIT compiling a process that is configured to be executed on both a source instruction set architecture and a destination instruction set architecture, mapping variables and address stacks of the process on both the source instruction set architecture and the destination instruction set architecture into a labeled form thereof, and mapping the labeled form of the variables and address stacks onto the destination instruction set architecture.

Claims

1. A method of live migration in a datacenter, wherein the method is performed under control of at least one hardware processor that is configured to execute instructions stored in a memory, the method comprising:

executing a process on a source instruction set architecture;

just-in-time (JIT) compiling the process,

wherein the JIT compiling includes;

performing a first JIT compilation of the process on the source instruction set architecture to generate a thin binary of the process, source variables, and function stacks of functions utilized by the thin binary on the source instruction set architecture;

storing, in accordance with the source instruction set architecture, the source variables and the function stacks of functions utilized by the thin binary on the source instruction set architecture;

performing a second JIT compilation of the process on a destination instruction set architecture to generate destination variables and function stacks of functions utilized by the thin binary on the destination instruction set architecture;

storing, in accordance with the destination instruction set architecture, the destination variables and the function stacks of functions utilized by the thin binary on the destination instruction set architecture; and

mapping the source and destination variables and address stacks of the thin binary from both the source instruction set architecture and the destination instruction set architecture into a labeled form by performing;

indirection dereferencing of source function addresses, from the function stacks of functions for the thin binary that executes on the source instruction set architecture, into a first lower level dictionary of the source instruction set architecture;

indirection dereferencing of source variable addresses, from the source variables for the thin binary that executes on the source instruction set architecture, into the first lower level dictionary of the source instruction set architecture;

indirection dereferencing of destination function addresses, from the function stacks of functions for the thin binary that executes on the destination instruction set architecture, into a second lower level dictionary stored on the destination instruction set architecture;

indirection dereferencing of destination variable addresses, from the destination variables for the thin binary that executes on the destination instruction set architecture, into the second lower level dictionary stored on the destination instruction set architecture; and

mapping, into the labeled form, the source function addresses and the source variable addresses to equivalent destination function addresses and destination variable addresses, and storing the mapped labeled form in a live migrator; and

migrating the thin binary between the source instruction set architecture and the destination instruction set architecture using the mapped labeled form,

wherein the mapping the source and destination variables and the address stacks of the thin binary facilitates transfer of state of the process, from the source instruction set architecture to the destination instruction set architecture, for migration of the thin binary between the source instruction set architecture and the destination instruction set architecture, using the mapped labeled form.

2. The method of claim 1, wherein the mapping the source and destination variables and the address stacks includes mapping names of variables and names of functions to objects thereof in respective low level databases of a JIT compiler.

3. The method of claim 1, wherein the source instruction set architecture includes an X86 instruction set architecture, and wherein the destination instruction set architecture includes an advanced reduced instruction set computer (RISC) machine (ARM) instruction set architecture.

4. The method of claim 1, wherein the source instruction set architecture and the destination instruction set architecture correspond to a common datacenter.

5. A non-transitory computer-readable medium that stores executable instructions that, in response to execution, cause a virtual machine manager to perform or control performance of operations comprising:

executing a process on a source instruction set architecture;

just-in-time (JIT) compiling the process, wherein the JIT compiling includes;

performing a first JIT compilation of the process on the source instruction set architecture to generate a thin binary of the process, source variables, and function stacks of functions utilized by the thin binary on the source instruction set architecture;

storing, in accordance with the source instruction set architecture, the source variables and the function stacks of functions utilized by the thin binary on the source instruction set architecture;

performing a second JIT compilation of the process on a destination instruction set architecture to generate destination variables and function stacks of functions utilized by the thin binary on the destination instruction set architecture;

storing, in accordance with the destination instruction set architecture, the destination variables and the function stacks of functions utilized by the thin binary on the destination instruction set architecture; and

mapping source and destination variables and address stacks of the thin binary from both the source instruction set architecture and the destination instruction set architecture into a labeled form by performing;

indirection dereferencing of source function addresses, from the function stacks of functions for the thin binary that executes on the source instruction set architecture, into a first lower level dictionary of the source instruction set architecture;

indirection dereferencing of source variable addresses, from the source variables for the thin binary that executes on the source instruction set architecture, into the first lower level dictionary of the source instruction set architecture;

indirection dereferencing of destination function addresses, from the function stacks of functions for the thin binary while executing on the destination instruction set architecture, into a second lower level dictionary stored on the destination instruction set architecture;

indirection dereferencing of destination variable addresses, from the destination variables for the thin binary while executing on the destination instruction set architecture, into the second lower level dictionary stored on the destination instruction set architecture; and

mapping, into a labeled form, the source function addresses and the source variable addresses to equivalent destination function addresses and destination variable addresses, and storing the mapped labeled form in a live migrator; and

migrating the thin binary between the source instruction set architecture and the destination instruction set architecture using the mapped labeled form,

wherein the mapping the source and destination variables and the address stacks of the thin binary facilitates transfer of state of the process, from the source instruction set architecture to the destination instruction set architecture, for migration of the thin binary between the source instruction set architecture and the destination instruction set architecture, using the map labeled form.

6. A live migrator, comprising:

means for executing a process on a source instruction set architecture;

means for just-in-time (JIT) compiling the process, wherein means for JIT compiling the process includes;

means for performing a first JIT compilation of the process on the source instruction set architecture to generate a thin binary of the process, source variables, and function stacks of functions utilized by the thin binary on the source instruction set architecture;

means for storing, in accordance with the source instruction set architecture, the source variables and the function stacks of functions utilized by the thin binary on the source instruction set architecture;

means for performing a second JIT compilation of the process on a destination instruction set architecture to generate destination variables and function stacks of functions utilized by the thin binary on the destination instruction set architecture;

means for storing, in accordance with the destination instruction set architecture, the destination variables and the function stacks of functions utilized by the thin binary on the destination instruction set architecture; and

means for mapping the source and destination variables and address stacks of the thin binary from both the source instruction set architecture and the destination instruction set architecture into a labeled form, wherein the means for mapping comprises;

means for indirection dereferencing source function addresses, from the function stacks of functions for the thin binary that executes on the source instruction set architecture, into a first lower level dictionary of the source instruction set architecture;

means for indirection dereferencing source variable addresses, from the source variables for the thin binary that executes on the source instruction set architecture, into the first lower level dictionary of the source instruction set architecture;

means for indirection dereferencing destination function addresses, from the function stacks of functions for the thin binary that executes on the destination instruction set architecture, into a second lower level dictionary stored on the destination instruction set architecture;

means for indirection dereferencing destination variable addresses, from the destination variables for the thin binary that executes on the destination instruction set architecture, into the second lower level dictionary stored on the destination instruction set architecture; and

means for mapping, into a labeled form, the source function addresses and the source variable addresses to equivalent destination function addresses and destination variable addresses and storage of the mapped labeled form in the live migrator; and

means for migrating of the thin binary between the source instruction set architecture and the destination instruction set architecture by use of the mapped labeled form,

wherein the map of the source and destination variables and the address stacks of the thin binary facilitates transfer of state of the process, from the source instruction set architecture to the destination instruction set architecture, for migrating the thin binary between the source instruction set architecture and the destination instruction set architecture, using the map labeled form.

7. The live migrator of claim 6, wherein:

the JIT compilation of the process includes production of an intermediate representation of the process on both the source instruction set architecture and the destination instruction set architecture, and

the map of the source and destination variables and the address stacks includes a map of variables and address stacks of the intermediate representation of the process from both the source instruction set architecture and the destination instruction set architecture into the labeled form thereof.

8. A live migrator, comprising:

a processor to execute a process on a source instruction set architecture; and

a just-in-time (JIT) compiler to JIT compile the process, wherein the JIT compilation of the process includes;

performance of a first JIT compilation of the process on the source instruction set architecture to generate a thin binary of the process, source variables, and function stacks of functions utilized by the thin binary on the source instruction set architecture;

storage of, in accordance with the source instruction set architecture, the source variables and the function stacks of functions utilized by the thin binary on the source instruction set architecture;

performance of a second JIT compilation of the process on a destination instruction set architecture to generate destination variables and function stacks of functions utilized by the thin binary on the destination instruction set architecture;

storage of, in accordance with the destination instruction set architecture, the destination variables and the function stacks of functions utilized by the thin binary on the destination instruction set architecture; and

map of the source and destination variables and address stacks of the thin binary from both the source instruction set architecture and the destination instruction set architecture into a labeled form by performance of;

indirection dereference of source function addresses, from the function stacks of functions for the thin binary that executes on the source instruction set architecture, into a first lower level dictionary of the source instruction set architecture;

indirection dereference of source variable addresses, from the source variables for the thin binary that executes on the source instruction set architecture, into the first lower level dictionary of the source instruction set architecture;

indirection dereference of destination function addresses, from the function stacks of functions for the thin binary that executes on the destination instruction set architecture, into a second lower level dictionary stored on the destination instruction set architecture;

indirection dereference of destination variable addresses, from the destination variables for the thin binary while executing on the destination instruction set architecture, into the second lower level dictionary stored on the destination instruction set architecture; and

map, into a labeled form, the source function addresses and the source variable addresses to equivalent destination function addresses and destination variable addresses and storage of the mapped labeled form in the live migrator,

wherein the processor is configured to migrate of the thin binary between the source instruction set architecture and the destination instruction set architecture by use of the mapped labeled form, and wherein the map of the source and destination variables and the address stacks of the thin binary facilitates transfer of state of the process, from the source instruction set architecture to the destination instruction set architecture, for migration of the thin binary between the source instruction set architecture and the destination instruction set architecture, using the map labeled form.