Hardware architecture for acceleration of computer vision and imaging processing
First Claim
1. A system, comprising:
- a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data;
a multi-port memory shared by the plurality of image processing hardware accelerators and configured to store the image data; and
an interconnection system configurably coupling the memory as a circular buffer to one or more of the image processing hardware accelerators and configured to process accesses of the image data by the image processing hardware accelerators,wherein for a first use case of the image processing hardware accelerators, two or more of the image processing hardware accelerators are configurably chained to operate in sequence in a first order,wherein for a second use case of the image processing hardware accelerators, one or more of the image processing hardware accelerators is configurably set to operate alone or chained to operate in sequence in a second order,wherein at least one of the image processing hardware accelerators is configurably allocated a portion of the memory based on whether the first use case or the second use case is configured, the allocated portion of the memory configured as part of the circular buffer, andwherein the interconnection system comprises;
a head pointer bus configured to carry a head pointer, which indicates a write progress, for the circular buffer;
a tail pointer bus configured to carry a tail pointer, which indicates a read progress, for the circular buffer;
a plurality of circular buffer write adapters configured to convert incoming image data into circular buffer data;
a plurality of circular buffer read adapters configured to convert circular buffer data into outgoing image data; and
at least one status bus that synchronizes circular buffer data access within the circular buffer, the at least one status bus communicates between the plurality of circular buffer write adapters and the plurality of circular buffer read adapters.
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Abstract
An image and vision processing architecture included a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data. A multi-port memory shared by the hardware accelerators stores the image data and is configurably coupled by a sparse crossbar interconnect to one or more of the hardware accelerators depending on a use case employed. The interconnect processes accesses of the image data by the hardware accelerators. Two or more of the hardware accelerators are chained to operate in sequence in a first order for a first use case, and at least one of the hardware accelerators is set to operate for a second use case. Portions of the memory are allocated to the hardware accelerators based on the use case employed, with an allocated portion of the memory configured as a circular buffer.
32 Citations
22 Claims
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1. A system, comprising:
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a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data; a multi-port memory shared by the plurality of image processing hardware accelerators and configured to store the image data; and an interconnection system configurably coupling the memory as a circular buffer to one or more of the image processing hardware accelerators and configured to process accesses of the image data by the image processing hardware accelerators, wherein for a first use case of the image processing hardware accelerators, two or more of the image processing hardware accelerators are configurably chained to operate in sequence in a first order, wherein for a second use case of the image processing hardware accelerators, one or more of the image processing hardware accelerators is configurably set to operate alone or chained to operate in sequence in a second order, wherein at least one of the image processing hardware accelerators is configurably allocated a portion of the memory based on whether the first use case or the second use case is configured, the allocated portion of the memory configured as part of the circular buffer, and wherein the interconnection system comprises; a head pointer bus configured to carry a head pointer, which indicates a write progress, for the circular buffer; a tail pointer bus configured to carry a tail pointer, which indicates a read progress, for the circular buffer; a plurality of circular buffer write adapters configured to convert incoming image data into circular buffer data; a plurality of circular buffer read adapters configured to convert circular buffer data into outgoing image data; and at least one status bus that synchronizes circular buffer data access within the circular buffer, the at least one status bus communicates between the plurality of circular buffer write adapters and the plurality of circular buffer read adapters. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method, comprising:
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for a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data, flexibly interconnecting the image processing hardware accelerators by chaining, for a first use case, two or more of the image processing hardware accelerators to operate in sequence in a first order, and setting, for a second use case, one or more of the image processing hardware accelerators to operate alone or chained to operate in sequence in a second order; for a multi-port memory shared by the plurality of image processing hardware accelerators and configured to store the image data, configuring a portion of the shared memory allocated to one of the image processing hardware accelerators as a circular buffer based on whether the first use case or the second use case is employed; and configuring an interconnection system coupling the memory to one or more of the image processing hardware accelerators to process accesses of the image data by the image processing hardware accelerators, wherein the interconnection system, comprises; a head pointer bus configured to carry a head pointer, which indicates write progress, for the circular buffer; a tail pointer bus configured to carry a tail pointer, which indicates read progress, for the circular buffer, a plurality of circular buffer write adapters configured to convert incoming image data into circular buffer data; a plurality of circular buffer read adapters configured to convert circular buffer data into outgoing image data; and at least one status bus that synchronizes circular buffer data access within the circular buffer, the at least one status bus communicates between the plurality of circular buffer write adapters and the plurality of circular buffer read adapters. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification