Routing conductors in an integrated display device and sensing device

• US 10,067,587 B2
• Filed: 12/29/2015
• Issued: 09/04/2018
• Est. Priority Date: 12/29/2015
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Shepelev, Petr
• Primary Examiner(s): MISHLER, ROBIN J
• Application Number:
  US14/983,218
• Publication Number:
  US 20170185197A1
• Time in Patent Office: 980 Days
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/041662 using alternate mutual and self-capacitive scanning
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: H10K 59/40 OLEDs integrated with touch screens

Abstract

An example display device includes an active portion having a plurality of display electrodes, an inactive portion, a plurality of source lines disposed at least partially in the active portion, and a plurality of routing traces. The routing traces include a first routing trace, at least a first portion thereof being disposed in a first metal layer, parallel to a first source line of the plurality of source lines and in the active portion. The routing traces further include a second routing trace, a first portion thereof disposed parallel to the first routing trace in the first metal layer and in the active portion, a second portion of the second routing trace disposed in a second metal layer in the inactive portion and crossing the first routing trace, the second routing trace coupled to a first display electrode of the plurality of display electrodes through a first via.

Claims

1. An input device including a capacitive sensing device integrated with a display device, the input device comprising:

a substrate;

a plurality of sensor electrodes of the capacitive sensing device, each of the plurality of sensor electrodes comprising one or more common electrodes of the display device;

a plurality of source lines disposed at least partially in an active portion of the display device; and

a plurality of routing traces, each of the plurality of routing traces uniquely couples a respective one of the plurality of sensor electrodes with a respective bond pad of a plurality of bond pads, wherein the plurality of routing traces includes;

a first routing trace, at least a first portion of the first routing trace being disposed in a first metal layer of the substrate, parallel to a first source line of the plurality of source lines and in the active portion of the display device; and

a second routing trace, a first portion of the second routing trace disposed parallel to the first routing trace in the first metal layer and in the active portion of the display device, a second portion of the second routing trace disposed in a second metal layer of the substrate in an inactive portion of the display device, crossing the first routing trace, and coupled to the first portion through a first via, the second routing trace coupled to a first sensor electrode of the plurality of sensor electrodes through a second via; and

a first bond pad disposed on one of the first metal layer, the second metal layer, and a third metal layer of the substrate, and coupled to the second portion to the second routing trace through a third via in the inactive portion.

2. The input device of claim 1, wherein the plurality of source lines is disposed in the first metal layer.

3. The input device of claim 1, wherein the plurality of source lines is disposed in the second metal layer.

4. The input device of claim 1, wherein the plurality of source lines is disposed in the third metal layer.

5. The input device of claim 1, further comprising a plurality of gate lines disposed in the second metal layer.

6. The input device of claim 5, wherein the plurality of source lines is disposed in one of the first metal layer or the third metal layer.

7. The input device of claim 1, further comprising a plurality of gate lines disposed in the third metal layer.

8. The input device of claim 7, wherein the plurality of source lines is disposed in one of the first metal layer or the second metal layer.

9. The input device of claim 1, wherein the first routing trace and the second routing trace are coupled to an integrated circuit, the integrated circuit is coupled to a first surface of the substrate via the first bond pad, and wherein the second portion of the second routing trace is located beneath the integrated circuit between the first surface and a second surface of the substrate.

10. The input device of claim 1, wherein the first routing trace is coupled to a second sensor electrode of the plurality of sensor electrodes through a fourth via.

11. The input device of claim 1, wherein at least one routing trace of the plurality of routing traces is coupled to an integrated circuit, wherein the integrated circuit is configured to drive the at least one routing trace with a guard signal.

12. The input device of claim 1, wherein each of the sensor electrodes and each of the plurality of routing traces is coupled to a respective pin of a plurality of pins of an integrated circuit.

24. The input device of claim 1 further comprising a second bond pad disposed on one of the first metal layer, the second metal layer, and the third meta layer, and coupled to the first routing trace through a fourth via in the inactive portion.

13. A display device, comprising:

a substrate having metal layers disposed thereon;

an active portion having a plurality of display electrodes;

an inactive portion;

a plurality of source lines disposed at least partially in the active portion; and

a plurality of routing traces, each of the plurality of routing traces uniquely couples a respective one of a plurality of sensor electrodes with a respective bond pad of a plurality of bond pads disposed on one of the metal layers, wherein the plurality of routing traces includes;

a first routing trace, at least a first portion of the first routing trace being disposed in a first metal layer of the metal layers, parallel to a first source line of the plurality of source lines and in the active portion; and

a second routing trace, a first portion of the second routing trace disposed parallel to the first routing trace in the first metal layer and in the active portion, a second portion of the second routing trace disposed in a second metal layer of the metal layers in the inactive portion, crossing the first routing trace, and coupled to the first portion through a first via, the second routing trace coupled to a first display electrode of the plurality of display electrodes through a first via,

wherein a first bond pad of the plurality of bond pads is coupled to the second portion of the second routing trace through a third via in the inactive portion.

14. The display device of claim 13, wherein the plurality of source lines is disposed in one of the first metal layer, the second metal layer or a third metal layer of the metal layers.

15. The display device of claim 13, further comprising a plurality of gate lines disposed in one of the second metal layer or a third metal layer of the metal layers.

16. The display device of claim 13, wherein the first routing trace and the second routing trace are coupled to an integrated circuit, the integrated circuit is coupled to a first surface of the substrate via the plurality of bond pads, and wherein the second portion of the second routing trace is located beneath the integrated circuit between the first surface and a second surface of the substrate.

17. The display device of claim 13, wherein the first routing trace is coupled to a second sensor electrode of the plurality of sensor electrodes through a fourth via.

18. The display device of claim 13, wherein at least one routing trace of the plurality of routing traces is coupled to an integrated circuit, wherein the integrated circuit is configured to drive the at least one routing trace with a guard signal.

19. The display device of claim 13, wherein each of the display electrodes and each of the plurality of routing traces is coupled to a respective pin of a plurality of pins of an integrated circuit.

20. A processing system for a capacitive sensing device and display device, the processing system comprising:

source drivers configured for driving a plurality of source lines disposed at least partially in an active portion of the display device; and

sensor circuitry configured to be coupled to a plurality of sensor electrodes of the capacitive sensing device through a plurality of routing traces, each of the plurality of sensor electrodes comprising one or more common electrodes of the display device, each of the plurality of routing traces uniquely couples a respective one of the plurality of sensor electrodes with a respective bond pad of a plurality of bond pads, wherein the plurality of routing traces includes;

a first routing trace, at least a first portion of the first routing trace being disposed in a first metal layer of a substrate, parallel to a first source line of the plurality of source lines and in the active portion of the display device;

a second routing trace, a first portion of the second routing trace disposed parallel to the first routing trace in the first metal layer and in the active portion of the display device, a second portion of the second routing trace disposed in a second metal layer of the substrate in an inactive portion of the display device, crossing the first routing trace, and coupled to the first portion through a first via the second routing trace coupled to a first sensor electrode of the plurality of sensor electrodes through a second via, the second portion of the second routing trace is coupled to a first bond pad through a third via in the inactive portion, wherein the first bond pad is disposed on one of the first metal layer, the second metal layer, and a third metal layer of the substrate.

21. The processing system of claim 20, wherein the plurality of source lines is disposed in one of the first metal layer, the second metal layer, or the third metal layer.

22. The processing system of claim 20, further comprising gate selection circuitry coupled to a plurality of gate lines disposed in one of the second metal layer or the third metal layer.

23. The processing system of claim 20, wherein the first routing trace is coupled to a second sensor electrode of the plurality of sensor electrodes through a fourth via.