Non-volatile ferroelectric memory cells with multilevel operation
First Claim
1. A method for storing multiple bits of information in a multi-level ferroelectric memory cell, comprising:
- receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer;
selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern;
applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern,wherein the ferroelectric multi-level memory cell is comprised of a ferroelectric capacitor or ferroelectric diode;
sensing a channel resistance of a second multi-level memory cell having a ferroelectric layer, wherein the second multi-level memory cell is the first multi-level memory cell;
determining a second bit pattern stored in the second multi-level memory cell based, at least in part, on the sensed resistance, wherein the sensed resistance of the second multi-level memory cell is representative of the remnant polarization of the ferroelectric layer; and
verifying the determined second bit pattern is the received bit pattern.
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Abstract
Ferroelectric components, such as the ferroelectric field effect transistors (FeFETs), ferroelectric capacitors and ferroelectric diodes described above may be operated as multi-level memory cells as described by the present invention. Storing multiple bits of information in each multi-level memory cell may be performed by a controller coupled to an array of the ferroelectric components configured as ferroelectric memory cells. The controller may execute the steps of receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer; selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern.
27 Citations
11 Claims
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1. A method for storing multiple bits of information in a multi-level ferroelectric memory cell, comprising:
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receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer; selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern, wherein the ferroelectric multi-level memory cell is comprised of a ferroelectric capacitor or ferroelectric diode; sensing a channel resistance of a second multi-level memory cell having a ferroelectric layer, wherein the second multi-level memory cell is the first multi-level memory cell; determining a second bit pattern stored in the second multi-level memory cell based, at least in part, on the sensed resistance, wherein the sensed resistance of the second multi-level memory cell is representative of the remnant polarization of the ferroelectric layer; and verifying the determined second bit pattern is the received bit pattern. - View Dependent Claims (2, 3, 4, 5)
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6. An apparatus, comprising:
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a) a memory cell comprising a ferroelectric capacitor or ferroelectric diode comprising; an upper electrode; a lower electrode; a blend of ferroelectric and semiconducting material between lower and upper electrode; and b) a controller coupled to the memory cell and configured to perform the steps of; i. receiving a bit pattern for writing to the memory cell; ii. selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; iii. applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern; iv. detecting a current through the memory cell; v. determining a bit pattern representative of the detected current vi. verify the determined bit pattern is equal to the received bit pattern. - View Dependent Claims (7, 8, 9, 10, 11)
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Specification