Semiconductor device, electronic component, and electronic device

• US 10,068,640 B2
• Filed: 01/25/2017
• Issued: 09/04/2018
• Est. Priority Date: 01/29/2016
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ishizu, Takahiko, Tamura, Hikaru
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): DINH, MINH D
• Application Number:
  US15/415,456
• Publication Number:
  US 20170221553A1
• Time in Patent Office: 587 Days
• Field of Search: 365 72
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

Claims

1. A semiconductor device comprising:

a processor core;

a memory section comprising a first memory comprising a memory cell; and

a bus,

wherein the memory cell comprises a first transistor, a second transistor, and a capacitor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the gate of the second transistor is electrically connected to a first terminal of the capacitor,

wherein the processor core is configured to generate a write enable signal,

wherein the bus is configured to output the write enable signal to the memory section,

wherein the first memory is configured to generate a wait signal on the basis of the write enable signal,

wherein the bus is configured to output the wait signal to the processor core,

wherein the processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal,

wherein n is an integer of 1 or more, and

wherein a write cycle time of the memory cell is longer than a read cycle time of the memory cell.

2. The semiconductor device according to claim 1, further comprising a third transistor, wherein a first terminal of the second transistor and a first terminal of the third transistor are electrically connected to each other.

3. The semiconductor device according to claim 1, wherein a channel formation region of the first transistor comprises an oxide semiconductor.

4. The semiconductor device according to claim 1, wherein the memory section comprises at least one of an SRAM, a flash memory, an ferroelectric RAM, a magnetoresistive RAM, a resistance RAM, and a phase change RAM.

5. An electronic component comprising:

a chip; and

a lead,

wherein the lead is electrically connected to the chip, and

wherein the semiconductor device according to claim 1 is provided in the chip.

6. An electronic device comprising:

the electronic component according to claim 5; and

at least one of a display portion, a touch sensor, a microphone, a speaker, an operation key, and a housing.

7. A semiconductor wafer comprising:

a plurality of first regions; and

a region for dicing,

wherein the semiconductor device according to claim 1 is provided in each of the first regions.

8. A semiconductor device comprising:

a processor core;

a memory section comprising a first memory comprising a memory cell;

a bus;

a register;

a clock generator; and

a logic section,

wherein the memory cell comprises a first transistor, a second transistor, and a capacitor,

wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,

wherein the gate of the second transistor is electrically connected to a first terminal of the capacitor,

wherein the processor core is configured to write first data to the register,

wherein the register is configured to output the first data to the clock generator and output the first data to the logic section,

wherein the clock generator is configured to generate a clock signal with frequency depending on the first data,

wherein the logic section is configured to generate a first signal on the basis of the first data and output the first signal to the first memory,

wherein the processor core is configured to generate a write enable signal,

wherein the bus is configured to output the write enable signal to the memory section,

wherein the first memory is configured to generate a wait signal on the basis of the write enable signal and the first signal,

wherein the bus is configured to output the wait signal to the processor core,

wherein the processor core is configured to delay access to the memory section by time form clock cycles, on the basis of the wait signal,

wherein m is an integer of 0 or more, and

wherein a write cycle time of the memory cell is longer than a read cycle time of the memory cell.

9. The semiconductor device according to claim 8, further comprising a third transistor, wherein a first terminal of the second transistor and a first terminal of the third transistor are electrically connected to each other.

10. The semiconductor device according to claim 8, wherein a channel formation region of the first transistor comprises an oxide semiconductor.

11. The semiconductor device according to claim 8, wherein the memory section comprises at least one of an SRAM, a flash memory, an ferroelectric RAM, a magnetoresistive RAM, a resistance RAM, and a phase change RAM.

12. An electronic component comprising:

a chip; and

a lead,

wherein the lead is electrically connected to the chip, and

wherein the semiconductor device according to claim 8 is provided in the chip.

13. An electronic device comprising:

the electronic component according to claim 12; and

at least one of a display portion, a touch sensor, a microphone, a speaker, an operation key, and a housing.

14. A semiconductor wafer comprising:

a plurality of first regions; and

a region for dicing,

wherein the semiconductor device according to claim 8 is provided in each of the first regions.