Processing a noisy analogue signal

• US 10,069,526 B2
• Filed: 04/14/2017
• Issued: 09/04/2018
• Est. Priority Date: 08/24/2012
• Status: Active Grant

• Current Assignee: Hanwha Phasor Limited
• Original Assignee: Phasor Solutions Limited (Hanwha Systems Co., Ltd.)
• Inventors: Mayo, Richard Hammond
• Primary Examiner(s): Le, Lana N
• Application Number:
  US15/488,130
• Publication Number:
  US 20170288715A1
• Time in Patent Office: 508 Days
• Field of Search: None
• CPC Class Codes: H04B 1/1081 Reduction of multipath noise by equalising H04B7/005
• CPC Class Codes: H04L 2027/0016 Stabilisation of local oscillators
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 27/227 using coherent demodulation

Abstract

A device is provided for correlating at least one noisy analog signal which is one of a plurality of signals obtained by a plurality of receivers. The device comprises a 1-bit quantization element to which is supplied, in use, the noisy signal; a comparator configured to compare the quantized signal with a reference signal which is a consensus signal obtained by averaging data from the plurality of receivers; and an up/down counter that is configured to be incremented by a subset of the comparison signal.

Claims

1. A method of correlating at least one noisy analog signal, wherein the at least one noisy analog signal is one of a plurality of signals obtained by a plurality of receivers;

the method comprising steps of;

1-bit quantising the at least one noisy analog signal to extract a 1-bit quantised noisy analog signal;

comparing the 1-bit quantised noisy analog signal with a quantised reference signal to result in a comparison signal, wherein the quantised reference signal is a consensus signal obtained by averaging data from the plurality of receivers; and

sampling the comparison signal to increment an up/down counter to identify correlation or a lack of correlation.

2. The method according to claim 1, comprising:

1-bit quantising each of in-phase and quadrature components of the at least one noisy analog signal;

comparing each of the quantised in-phase and quadrature components of the at least one noisy analog signal with each of quantised in-phase and quadrature components of the quantised reference signal;

if the quantised in-phase components of the at least one noisy analog signal and the quantised reference signal are equal, incrementing or decrementing a first up/down counter in a first direction and, if not, incrementing or decrementing the first up/down counter in a second direction;

if the quantised quadrature components of the at least one noisy analog signal and the quantised reference signal are equal, incrementing or decrementing the first up/down counter in the first direction and, if not, incrementing or decrementing the first up/down counter in the second direction;

if the quantised in-phase component of the at least one noisy analog signal and the quantised quadrature component of the quantised reference signal are equal, incrementing or decrementing a second up/down counter in a first direction and, if not, incrementing or decrementing the second up/down counter in a second direction; and

if the quantised quadrature component of the at least one noisy analog signal and the quantised in-phase component of the quantised reference signal are equal, incrementing or decrementing the second up/down counter in the second direction and, if not, incrementing or decrementing the second up/down counter in the first direction.

3. The method according to claim 2, comprising:

stopping the first and second up/down counters when one of the first and second up/down counters reaches full scale.

4. The method according to claim 2, comprising:

determining a phase offset between a phase of the 1-bit quantised noisy analog signal and the phase of the quantised reference signal by considering the values of the first and second up/down counters;

altering the phase of the 1-bit quantised noisy analog signal in order to correct for the phase offset; and

resetting the first and second up/down counters.

5. The method according to claim 1, comprising inverting the 1-bit quantised noisy analog signal if there is a strong negative correlation.

6. The method according to claim 1, comprising excluding the 1-bit quantised noisy analog signal from the consensus signal if the 1-bit quantised noisy analog signal consistently sits beyond a predetermined range of the consensus signal.

7. A device for correlating at least one noisy analog signal, wherein the at least one noisy analog signal is one of a plurality of signals obtained by a plurality of receivers, the device comprising:

a 1-bit quantisation element for receiving the at least one noisy analog signal to extract a 1-bit quantised noisy analog signal;

a comparator configured to compare the 1-bit quantised noisy analog signal with a quantised reference signal to result in a comparison signal, wherein the quantised reference signal is a noisy signal and is a consensus signal obtained by averaging data from the plurality of receivers; and

an up/down counter that is configured to be incremented by a subset of the comparison signal to identify correlation or a lack of correlation.

8. The device according to claim 7, further comprising a sampling device, wherein the sampling device samples the comparison signal, and wherein the up/down counter increments each time that the sampling device samples the comparison signal.

9. The device according to claim 7, comprising an oscillator configured to modify a phase of the 1-bit quantised noisy analog signal.

10. The device according to claim 7, wherein the comparator is an XOR gate.

11. The device according to claim 7, wherein:

the 1-bit quantisation element is configured to receive the at least one noisy analog signal and to extract a 1-bit quantised noisy analog signal for each of in-phase and quadrature components of the at least one noisy analog signal;

the comparator is configured to compare each of the quantised in-phase and quadrature components of the at least one noisy analog signal with each of quantised in-phase and quadrature components of the quantised reference signal; and

the device comprises first and second up/down counters, wherein;

if the quantised in-phase components of the at least one noisy analog signal and the quantised reference signal are equal, the first up/down counter is configured to be incremented or decremented in a first direction and, if not, the first up/down counter is configured to be incremented or decremented in a second direction;

if the quantised quadrature components of the at least one noisy analog signal and the quantised reference signal are equal, the first up/down counter is configured to be incremented or decremented in the first direction and, if not, the first up/down counter is configured to be incremented or decremented in the second direction;

if the quantised in-phase component of the at least one noisy analog signal and the quantised quadrature component of the quantised reference signal are equal, the second up/down counter is configured to be incremented or decremented in a first direction and, if not, the second up/down counter is configured to be incremented or decremented in a second direction; and

if the quantised quadrature component of the at least one noisy analog signal and the quantised in-phase component of the quantised reference signal are equal, the second up/down counter is configured to be incremented or decremented in the second direction and, if not, the second up/down counter is configured to be incremented or decremented in the first direction.

12. The device according to claim 11, wherein:

the first and second up/down counters are configured to be stopped when one of the first and second up/down counters reaches full scale.

13. The device according to claim 11, wherein:

the device is configured to determine a phase offset between a phase of the 1-bit quantised noisy analog signal and a phase of the quantised reference signal from the values of the first and second up/down counters and

the device comprises;

a control block for receiving the identified correlation or lack of correlation and

an oscillator which alters the phase of the 1-bit quantised noisy analog signal in order to correct for the phase offset determined from the control block.

14. The device according to claim 7, comprising a control block having a power on reset facility configured to reset the or each up/down counter.

15. The device according to claim 7, comprising an inverting element comprising at least one XOR gate configured to invert the 1-bit quantised noisy analog signal if there is a strong negative correlation.

16. The device according to claim 7, comprising a control circuit configured to exclude the at least one noisy analog signal from the consensus signal if the at least one noisy analog signal consistently sits beyond a predetermined range of the consensus signal.

17. Apparatus comprising the plurality of receivers, each of the plurality of receivers comprising the device according to claim 7.