Alignment testing for tiered semiconductor structure
First Claim
1. A method for evaluating a tiered semiconductor structure, comprising:
- evaluating connectivity, through a conductive arc within a first layer of a tiered semiconductor structure, between a first via, a second via, and a third via of a second layer of the tiered semiconductor structure to determine an alignment rotation, wherein the evaluating connectivity comprises;
transmitting a first test signal through the first via and measuring a response at the second via and the third via to yield first results, andtransmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results;
evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation; and
invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure.
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Abstract
Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
13 Citations
20 Claims
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1. A method for evaluating a tiered semiconductor structure, comprising:
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evaluating connectivity, through a conductive arc within a first layer of a tiered semiconductor structure, between a first via, a second via, and a third via of a second layer of the tiered semiconductor structure to determine an alignment rotation, wherein the evaluating connectivity comprises; transmitting a first test signal through the first via and measuring a response at the second via and the third via to yield first results, and transmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results; evaluating the tiered semiconductor structure for misalignment based upon the alignment rotation; and invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for evaluating a tiered semiconductor structure, comprising:
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evaluating connectivity within a first arc segment of a conductive arc, wherein; the conductive arc is within a first layer of a tiered semiconductor structure and the connectivity is evaluated between a set of vias within a second layer of the tiered semiconductor structure, and the evaluating connectivity comprises; transmitting a first test signal through a first via of the set of vias and measuring a response at a second via of the set of vias adjacent to the first via and a third via of the set of vias adjacent to the second via to yield first results, and transmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results; responsive to determining that the first via has connectivity through the first arc segment to the second via, that the first via does not have connectivity to the third via, and that the second via does not have connectivity to the third via, determining a counterclockwise alignment rotation; evaluating the tiered semiconductor structure for misalignment based upon the counterclockwise alignment rotation; and invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure. - View Dependent Claims (10, 11, 12, 13, 20)
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14. A method for evaluating a tiered semiconductor structure, comprising:
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evaluating connectivity within a first arc segment of a conductive arc, wherein; the conductive arc is within a first layer of a tiered semiconductor structure and the connectivity is evaluated between a set of vias within a second layer of the tiered semiconductor structure, and the evaluating connectivity comprises; transmitting a first test signal through a first via of the set of vias and measuring a response at a second via of the set of vias adjacent to the first via and a third via of the set of vias adjacent to the second via to yield first results, and transmitting a second test signal through the second via and measuring a response at the first via and the third via to yield second results; responsive to determining that the third via has connectivity through the first arc segment to the second via, that the first via does not have connectivity to the third via, and that the first via does not have connectivity to the second via, determining a clockwise alignment rotation value; evaluating the tiered semiconductor structure for misalignment based upon the clockwise alignment rotation value; and invoking at least one of a testing unit, a repair unit, or a fault tolerance unit to process one or more tiers during stacked CMOS production processing of the tiered semiconductor structure. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification