Processors having virtually clustered cores and cache slices

• US 10,073,779 B2
• Filed: 12/28/2012
• Issued: 09/11/2018
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Daedalus Prime LLC (Daedalus Group LLC)
• Original Assignee: Intel Corporation
• Inventors: Hum, Herbert H., Ganesh, Brinda, Vash, James R., Kumar, Ganesh, Puthiyedath, Leena K., Erlanger, Scott J., Dehaemer, Eric J., Moga, Adrian C., Sebot, Michelle M., Carlson, Richard L., Bubien, David, Delano, Eric
• Primary Examiner(s): Bansal, Gurtej
• Application Number:
  US13/729,579
• Publication Number:
  US 20140189239A1
• Time in Patent Office: 2,083 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache

Abstract

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Claims

1. A processor comprising:

a plurality of logical processors each having one or more corresponding lower level caches;

a shared higher level cache that is to be shared by the plurality of logical processors, in which the shared higher level cache includes a physically distributed cache slice that is physically distributed across a die for each of the plurality of logical processors, wherein the physically distributed cache slices are physically separated from one another on the die; and

logic to direct a missed access in one or more lower level caches of a corresponding given logical processor initially to only a first subset of the physically distributed cache slices of the shared higher level cache of a first virtual cluster that includes at least two of the plurality of logical processors including the given logical processor, wherein the first virtual cluster does not include a second subset of the physically distributed cache slices of the shared higher level cache that are included in a second virtual cluster that includes at least two of the plurality of logical processors.

2. The processor of claim 1, wherein the first virtual cluster includes a same number of cache slices as the second virtual cluster, and wherein a cache slice of the first virtual cluster is shared by said at least two of the plurality of logical processors.

3. The processor of claim 1, wherein the first virtual cluster includes predominantly proximally physically located logical processors that are closer on average to one another than they are to logical processors of the second virtual cluster.

4. The processor of claim 1, wherein the first virtual cluster includes predominantly logical processors directly coupled to a common interconnect structure, and wherein the second virtual cluster predominantly logical processors directly coupled to a different common interconnect structure.

5. The processor of claim 1, wherein the processor is to reduce a power consumption state of the first virtual cluster without reducing a power consumption state of the second virtual cluster.

6. The processor of claim 1, wherein most logical processors of the first virtual cluster are directly coupled to a first ring interconnect and at least one logical processor of the first virtual cluster is directly coupled to a second ring interconnect.

7. The processor of claim 1, wherein the plurality of logical processors are monolithically integrated on a semiconductor substrate, and wherein the plurality of logical processors comprise at least twelve cores.

8. The processor of claim 1, wherein the virtual cluster includes a plurality of sub-clusters that each are to include a subset of the physically distributed cache slices of the virtual cluster.

9. The processor of claim 1, wherein the first virtual cluster includes a corresponding cache coherency aware memory controller.

10. The processor of claim 9, wherein, if the missed access misses in the first subset of the physically distributed cache slices in the first virtual cluster, the missed access is directed to the cache coherency aware memory controller corresponding to the first virtual cluster.

11. The processor of claim 10, wherein the cache coherency aware memory controller is able to snoop cache slices in one or more other virtual clusters to attempt to service the missed access.

12. The processor of claim 1, wherein the processor has two virtual clusters, wherein each logical processor of each of the two virtual clusters has a corresponding logical processor identifier, and wherein a single bit in a corresponding position in each of the logical processor identifiers is used to identify which of the two virtual clusters the corresponding logical processor is in.

13. The processor of claim 12, wherein the logical processor identifiers are derived from a hash.

14. A method comprising:

virtually clustering a first plurality of logical processors, including a given logical processor, into a first virtual cluster;

virtually clustering a second plurality of logical processors into a second virtual cluster, in which each of the first and second pluralities of logical processors has one or more corresponding lower level caches; and

directing an access that misses in one or more lower level caches corresponding to the given logical processor initially to only a first subset of physically distributed cache slices, of a shared higher level cache, that are in the first virtual cluster that corresponds to the given logical processor, wherein the first virtual cluster does not include a second subset of the physically distributed cache slices, of the shared higher level cache, that correspond to the second virtual cluster, and wherein each of the physically distributed cache slices in the first subset is physically co-located on a die with a different one of the first plurality of logical processors, and each of the physically distributed cache slices in the second subset is physically co-located on the die with a different one of the second plurality of logical processors.

15. The method of claim 14, wherein the first virtual cluster has a same number of cache slices as the second virtual cluster.

16. The method of claim 14, wherein the first virtual cluster includes predominantly proximally physically located logical processors that are closer on average to one another than they are to logical processors of the second virtual cluster.

17. The method of claim 14, wherein the first virtual cluster includes predominantly logical processors that are directly coupled to a common interconnect structure, and wherein the second virtual cluster includes predominantly logical processors that are directly coupled to a different common interconnect structure.

18. The method of claim 14, wherein the processor has two virtual clusters, wherein each logical processor of each of the two virtual clusters by a corresponding logical processor identifier, and further comprising using a single bit that is in a same corresponding position in each of the logical processor identifiers to identify which of the two virtual clusters the corresponding logical processor is in.

19. The method of claim 14, further comprising reducing a power consumption state of the first virtual cluster without reducing a power consumption state of the second virtual cluster.

20. The method of claim 14, wherein the first virtual cluster has a corresponding cache coherency aware memory controller, and further comprising, if the access misses in the first subset of the physically distributed cache slices in the first virtual cluster, directing the access to the cache coherency aware memory controller corresponding to the first virtual cluster.

21. The method of claim 20, further comprising the cache coherency aware memory controller snooping cache slices in one or more other virtual clusters to attempt to service the access.