Deep trench isolation for RF devices on SOI

• US 10,074,650 B2
• Filed: 05/03/2016
• Issued: 09/11/2018
• Est. Priority Date: 12/27/2013
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Huang, Herb He, Li, Haiting, Jin, Xingcheng, Wang, Xinxue, Zhao, Hongbo, Chen, Fucheng, Xiang, Yanghui
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US15/145,776
• Publication Number:
  US 20160247801A1
• Time in Patent Office: 861 Days
• Field of Search: 257347, 257374, 257501, 257525, 257524, 257526, 257E2141, 257E21002, 438205, 438309, 438381
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2

Abstract

A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The semiconductor device also includes a plurality of transistors on the second semiconductor substrate, a deep trench isolation having a bottom at a surface of the first semiconductor substrate in the second region, the deep trench isolation exposing a sidewall of the second semiconductor substrate and a sidewall of the buried insulating layer, and a dielectric capping layer filling the deep trench isolation and covering the plurality of transistors on the second semiconductor substrate.

Claims

1. A semiconductor device comprising:

a silicon-on-insulator (SOI) substrate having a first region and a second region, the SOI substrate including a vertical stack of a first semiconductor substrate, a buried insulating layer, and a second semiconductor substrate arranged from bottom to top in the first region, respectively;

a plurality of transistors on the second semiconductor substrate;

a deep trench isolation having a bottom at a surface of the first semiconductor substrate in the second region, the deep trench isolation exposing a sidewall of the second semiconductor substrate and a sidewall of the buried insulating layer; and

a homogeneous dielectric capping layer filling the deep trench isolation and covering the plurality of transistors on the second semiconductor substrate.

2. The semiconductor device of claim 1, wherein the dielectric capping layer comprises silicon nitride.

3. The semiconductor device of claim 1, wherein each of the transistors comprises a gate electrode, source/drain regions disposed on opposite of the gate electrode, and a metal silicide formed on a surface of the gate electrode and the source/drain regions.

4. The semiconductor device of claim 1, further comprising an ion implanted layer disposed at the bottom of the deep trench isolation.

5. The semiconductor device of claim 4, wherein the ion implanted layer comprises argon or boron.

6. A semiconductor device comprising:

a silicon-on-insulator (SOI) substrate having a first region and a second region, the SOI substrate including a vertical stack of a first semiconductor substrate, a buried insulating layer, and a second semiconductor substrate arranged from bottom to top in the first region, respectively;

a plurality of transistors on the second semiconductor substrate;

a deep trench isolation having a bottom at a surface of the first semiconductor substrate in the second region, the deep trench isolation exposing a sidewall of the second semiconductor substrate and a sidewall of the buried insulating layer;

a dielectric capping layer filling the deep trench isolation; and

an ion implanted region abutting to the buried insulating layer.

7. The semiconductor device of claim 6, wherein the ion implanted layer comprises argon or boron.

8. The semiconductor device of claim 6, wherein each of the plurality of transistors comprises a gate electrode, source/drain regions disposed on opposite of the gate electrode, and a metal silicide formed on a surface of the gate electrode and the source/drain regions.

9. The semiconductor device of claim 8, wherein the dielectric capping layer covers the gate electrode, and the source/drain regions of plurality of transistors.

10. The semiconductor device of claim 6, wherein the dielectric capping layer comprises silicon nitride.