Adjusting access of non-volatile semiconductor memory based on access time

• US 10,079,048 B2
• Filed: 03/24/2009
• Issued: 09/18/2018
• Est. Priority Date: 03/24/2009
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Syu, Mei-Man L.
• Primary Examiner(s): Nam, Hyun
• Assistant Examiner(s): Phan, Dean
• Application Number:
  US12/410,304
• Publication Number:
  US 20100250793A1
• Time in Patent Office: 3,465 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A non-volatile semiconductor memory is disclosed comprising a first memory device and control circuitry operable to issue an access command to the first memory device. A command status is requested from the first memory device after a status delay. When the command status indicates the first memory device has completed the command, a first access time of the memory device is measured. An access sequence of the first memory device is then modified in response to the access time.

Claims

1. A non-volatile semiconductor memory comprising a first memory device, a second memory device, and control circuitry operable to:

measure a first access time of the first memory device following issuance of a first access command to the first memory device;

measure a second access time of the second memory device following issuance of a second access command to the second memory device, wherein the second access command is issued after the first access command according to an access order of the first and second memory devices, wherein the access order defines a sequence of accessing the first and second memory devices for consecutive access commands;

modify the access order of the first and second memory devices for subsequent consecutive access commands based on the measured first and second access times; and

set a delay period of the subsequent consecutive access command associated with the first memory device, wherein the delay period is based on the first access time and indicates when a polling for a status of the subsequent consecutive access command begins after the subsequent consecutive access command is issued.

2. The non-volatile semiconductor memory as recited in claim 1, wherein the control circuitry is further operable to access the first and second memory devices over a shared bus.

3. The non-volatile semiconductor memory as recited in claim 2, wherein the control circuitry is further operable to modify the access order of the first and second memory devices for subsequent access commands by modifying an order in which the control circuitry transmits access commands to the first and second memory devices over the shared bus.

4. The non-volatile semiconductor memory as recited in claim 3, wherein the control circuitry is further operable to:

first select one of the first and second memory devices in response to the first and second access times;

transmit a third access command to the first selected memory device;

second select a different one of the first and second memory devices in response to the first and second access times; and

after transmitting the third access command to the first selected memory device and during an access time associated with the first selected memory device for the third access command, transmit a fourth access command to the second selected memory device.

5. The non-volatile semiconductor memory as recited in claim 4, wherein the access time of the first selected memory device is less than the access time of the second selected memory device.

11. The non-volatile semiconductor memory as recited in claim 1, wherein modifying the access order further comprises:

modify the access order such that the first memory device is before the second memory device if the first access time is less than the second access time; and

modify the access order such that the second memory device is before the first memory device if the second access time is less than the first access time.

6. A method of operating a non-volatile semiconductor memory comprising a first memory device and a second memory device, the method comprising:

issuing an access command to the first memory device;

requesting a command status from the first memory device after a status delay;

when the command status indicates the first memory device has completed the access command, measuring a first access time of the first memory device;

measuring a second access time of the second memory device;

modifying, based on the first and second access times, an order in which subsequent access commands are issued to the first and second memory devices such that the first memory device is before the second memory device in the order if the first access time is less than the second access time and the second memory device is before the first memory device in the order if the second access time is less than the first access time, wherein the order defines a sequence of accessing the first and second memory devices for consecutive access commands; and

setting a delay period of the subsequent consecutive access command associated with the first memory device, wherein the delay period is based on the first access time and indicates when a polling for a status of the subsequent consecutive access command begins after the subsequent consecutive access command is issued.

7. The method as recited in claim 6, further comprising accessing the first and second memory devices over a shared bus.

8. The method as recited in claim 7, further comprising modifying the order in which the subsequent access commands are issued to the first and second memory devices by modifying an order in which commands are transmitted to the first and second memory devices over the shared bus.

9. The method as recited in claim 8, further comprising:

first selecting one of the first and second memory devices in response to the first and second access times;

transmitting a third access command to the first selected memory device;

second selecting a different one of the first and second memory devices in response to the first and second access times; and

after transmitting the third access command to the first selected memory device and during an access time associated with the first selected memory device for the third access command, transmitting a fourth access command to the second selected memory device.

10. The method as recited in claim 9, wherein the access time of the first selected memory device is less than the access time of the second selected memory device.

12. A method comprising:

determining a first access sequence for a first memory device and a second memory device, wherein the first memory device is before the second memory device in the first access sequence;

determining a first access time of the first memory device;

determining a second access time of the second memory device;

determining that the second access time is less than the first access time;

modifying, in response to determining the second access time is less than the first access time, the first access sequence to a second access sequence, wherein the second memory device is before the first memory device in the second access sequence, and the second access sequence defines a sequence of accessing the first and second memory devices for consecutive access commands; and

setting a delay period of the consecutive access command associated with the first memory device, wherein the delay period is based on the first access time and indicates when a polling for a status of the consecutive access command begins after the consecutive access command is issued.