Thin film transistor array substrate and display panel

• US 10,083,664 B1
• Filed: 05/04/2018
• Issued: 09/25/2018
• Est. Priority Date: 12/31/2014
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Du, Peng, Shih, Ming-Hung, Kang, Chih-Tsung, Hsu, Je-Hao, Lv, Qibiao
• Primary Examiner(s): Mehmood, Jennifer
• Assistant Examiner(s): SUBEDI, DEEPROSE D
• Application Number:
  US15/971,219
• Publication Number:
  US 20180254011A1
• Time in Patent Office: 144 Days
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0447 for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A thin film transistor (TFT) array substrate and a display panel are provided. The TFT array substrate includes multiple pixels arranged in an array. Each pixel includes first through third sub-pixels sequentially arranged along a first direction. The first through third sub-pixels are connected to a same scan line. The TFT array substrate further includes first through third data lines sequentially arranged along the first direction. The first through third data lines respectively are for driving the first through third sub-pixels. The first sub-pixel includes first and second areas, the second sub-pixel includes third and fourth areas, and the third sub-pixel includes fifth and sixth areas, arranged along a second direction. A voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode.

Claims

1. A thin film transistor array substrate, comprising a plurality of pixels arranged in an array,

wherein each of the plurality of pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel sequentially arranged in a first direction, the first sub-pixel, the second sub-pixel and the third sub-pixel being connected to a same scan line;

the thin film transistor array substrate further comprises a first data line, a second data line and a third data line sequentially arranged in the first direction, the first data line being configured for driving the first sub-pixel, the second data line being configured for driving the second sub-pixel, the third data line being configured for driving the third sub-pixel; and

the first sub-pixel comprises a first area and a second area arranged in a second direction;

the second sub-pixel comprises a third area and a fourth area arranged in the second direction;

the third sub-pixel comprises a fifth area and a sixth area arranged in the second direction;

wherein a voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode;

wherein the thin film transistor array substrate further comprises a fourth data line, the third data line being configured for driving the fifth area of the third sub-pixel, the fourth data line being configured for the sixth area of the third sub-pixel, wherein a driving voltage applied onto the third data line is different from a driving voltage applied onto the fourth data line; and

wherein the first area comprises a first thin film transistor disposed therein;

the second area comprises a second thin film transistor disposed therein;

the third area comprises a third thin film transistor disposed therein;

the fourth area comprises a fourth thin film transistor disposed therein;

the fifth area comprises a fifth thin film transistor disposed therein; and

the sixth area has a sixth thin film transistor disposed therein, wherein gates of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are connected to the same scan line;

drains of the first thin film transistor and the second thin film transistor are connected to the first data line;

a source of the first thin film transistor sequentially connects a first main sub-pixel electrode and a first capacitor to the common electrode;

a source of the second thin film transistor sequentially connects a first subsidiary sub-pixel electrode and a second capacitor to the common electrode;

drains of the third thin film transistor and the fourth thin film transistor are connected to the second data line;

a source of the third thin film transistor sequentially connects a second main sub-pixel electrode and a third capacitor to the common electrode;

a source of the fourth thin film transistor sequentially connects a second subsidiary sub-pixel electrode and a fourth capacitor to the common electrode;

a drain of the fifth thin film transistor is connected to the third data line;

a source of the fifth thin film transistor sequentially connects a third main sub-pixel electrode and a fifth capacitor to the common electrode;

a drain of the sixth thin film transistor is connected to the fourth data line;

a source of the sixth thin film transistor sequentially connects a third subsidiary sub-pixel electrode and a sixth capacitor to the common electrode.

2. The thin film transistor array substrate as claimed in claim 1, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

3. The thin film transistor array substrate as claimed in claim 1, wherein a voltage difference between a sub-pixel electrode in the fourth area and the common electrode is different from a voltage difference between a sub-pixel electrode in the third area and the common electrode.

4. The thin film transistor array substrate as claimed in claim 3, wherein the four area has an additional thin film transistor disposed therein;

a gate of the additional thin film transistor is connected to the scan line;

a drain of the additional thin film transistor is connected to a second subsidiary sub-pixel electrode; and

a source of the additional thin film transistor is connected to the common electrode.

5. A thin film transistor array substrate, comprising a plurality of pixels arranged in an array,

wherein each of the plurality of pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel sequentially arranged in a first direction, the first sub-pixel, the second sub-pixel and the third sub-pixel being connected to a same scan line;

the thin film transistor array substrate further comprises a first data line, a second data line and a third data line sequentially arranged in the first direction, the first data line being configured for driving the first sub-pixel, the second data line being configured for driving the second sub-pixel, the third data line being configured for driving the third sub-pixel; and

the first sub-pixel comprises a first area and a second area arranged in a second direction;

the second sub-pixel comprises a third area and a fourth area arranged in the second direction;

the third sub-pixel comprises a fifth area and a sixth area arranged in the second direction;

wherein a voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode;

wherein the thin film transistor array substrate further comprises a fourth data line, the third data line being configured for driving the fifth area of the third sub-pixel, the fourth data line being configured for the sixth area of the third sub-pixel, wherein a driving voltage applied onto the third data line is different from a driving voltage applied onto the fourth data line;

wherein the thin film transistor array substrate further comprises a fifth data line, the second data line being configured for driving the third area of the second sub-pixel, the fifth data line being configured for driving the fourth area of the second sub-pixel, wherein a driving voltage applied onto the second data line is different from a driving voltage applied onto the fifth data line.

6. The thin film transistor array substrate as claimed in claim 5, wherein the first area comprises a first thin film transistor disposed therein;

the second area comprises a second thin film transistor disposed therein;

the third area has a third thin film transistor disposed therein, the fourth area has a fourth thin film transistor disposed therein, the fifth area has a fifth thin film transistor disposed therein, and the sixth area has a sixth thin film transistor disposed therein;

gates of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are connected to the same scan line, drains of the first thin film transistor and the second thin film transistor are connected to the first data line, a source of the first thin film transistor sequentially connects a first main sub-pixel electrode and a first capacitor to the common electrode, a source of the second thin film transistor sequentially connects a first subsidiary sub-pixel electrode and a second capacitor to the common electrode;

a source of the third thin film transistor sequentially connects a second main sub-pixel electrode and a third capacitor to the common electrode, a drain of the third thin film transistor is connected to the second data line, a source of the fourth thin film transistor sequentially connects a second subsidiary sub-pixel electrode and a fourth capacitor to the common electrode, a drain of the fourth thin film transistor is connected to the fifth data line;

a drain of the fifth thin film transistor is connected to the third data line, a source of the fifth thin film transistor sequentially connects a third main sub-pixel electrode and a fifth capacitor to the common electrode, a drain of the sixth thin film transistor is connected to the fourth data line, and a source of the sixth thin film transistor sequentially connects a third subsidiary sub-pixel electrode and a sixth capacitor to the common electrode.

7. The thin film transistor array substrate as claimed in claim 5, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

8. A display panel comprising a thin film transistor array substrate having a plurality of pixels arranged in an array,

wherein each of the plurality of pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel sequentially arranged in a first direction, the first sub-pixel, the second sub-pixel and the third sub-pixel being connected to a same scan line;

the thin film transistor array substrate further comprises a first data line, a second data line and a third data line sequentially arranged in the first direction, the first data line being configured for driving the first sub-pixel, the second data line being configured for driving the second sub-pixel, the third data line being configured for driving the third sub-pixel; and

the first sub-pixel comprises a first area and a second area arranged in a second direction;

the second sub-pixel comprises a third area and a fourth area arranged in the second direction; and

the third sub-pixel comprises a fifth area and a sixth area arranged in the second direction; and

wherein a voltage difference between a sub-pixel electrode in the sixth area and a common electrode is different from a voltage difference between a sub-pixel electrode in the fifth area and the common electrode;

wherein the thin film transistor array substrate further comprises a fourth data line, the third data line being configured for driving the fifth area of the third sub-pixel, the fourth data line being configured for the sixth area of the third sub-pixel, wherein a driving voltage applied onto the third data line is different from a driving voltage applied onto the fourth data line;

wherein the thin film transistor array substrate further comprises a fifth data line, the second data line being configured for driving the third area of the second sub-pixel, the fifth data line being configured for driving the fourth area of the second sub-pixel, wherein a driving voltage applied onto the second data line is different from a driving voltage applied onto the fifth data line.

9. The display panel as claimed in claim 8, wherein the first area comprises a first thin film transistor disposed therein;

the second area comprises a second thin film transistor disposed therein;

the third area has a third thin film transistor disposed therein, the fourth area has a fourth thin film transistor disposed therein, the fifth area has a fifth thin film transistor disposed therein, and the sixth area has a sixth thin film transistor disposed therein;

gates of the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are connected to the same scan line, drains of the first thin film transistor and the second thin film transistor are connected to the first data line, a source of the first thin film transistor sequentially connects a first main sub-pixel electrode and a first capacitor to the common electrode, a source of the second thin film transistor sequentially connects a first subsidiary sub-pixel electrode and a second capacitor to the common electrode;

a source of the third thin film transistor sequentially connects a second main sub-pixel electrode and a third capacitor to the common electrode, a drain of the third thin film transistor is connected to the second data line, a source of the fourth thin film transistor sequentially connects a second subsidiary sub-pixel electrode and a fourth capacitor to the common electrode, a drain of the fourth thin film transistor is connected to the fifth data line;

a drain of the fifth thin film transistor is connected to the third data line, a source of the fifth thin film transistor sequentially connects a third main sub-pixel electrode and a fifth capacitor to the common electrode, a drain of the sixth thin film transistor is connected to the fourth data line, and a source of the sixth thin film transistor sequentially connects a third subsidiary sub-pixel electrode and a sixth capacitor to the common electrode.

10. The display panel as claimed in claim 8, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.